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arm: Clarify the logic of set_pc()
Until now, the set_pc logic was unclear, which raised questions about whether it should be used directly, applying a value to PC or adding additional checks, for example, set the Thumb bit in Arm cpu. Let's set the set_pc logic for “Configure the PC, as was done in the ELF file” and implement synchronize_with_tb hook for preserving PC to cpu_tb_exec. Backports commit 42f6ed919325413392bea247a1e6f135deb469cd from qemu
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@ -95,9 +95,21 @@ struct TranslationBlock;
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* @get_arch_id: Callback for getting architecture-dependent CPU ID.
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* @get_paging_enabled: Callback for inquiring whether paging is enabled.
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* @get_memory_mapping: Callback for obtaining the memory mappings.
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* @set_pc: Callback for setting the Program Counter register.
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* @set_pc: Callback for setting the Program Counter register. This
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* should have the semantics used by the target architecture when
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* setting the PC from a source such as an ELF file entry point;
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* for example on Arm it will also set the Thumb mode bit based
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* on the least significant bit of the new PC value.
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* If the target behaviour here is anything other than "set
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* the PC register to the value passed in" then the target must
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* also implement the synchronize_from_tb hook.
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* @synchronize_from_tb: Callback for synchronizing state from a TCG
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* #TranslationBlock.
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* #TranslationBlock. This is called when we abandon execution
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* of a TB before starting it, and must set all parts of the CPU
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* state which the previous TB in the chain may not have updated.
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* This always includes at least the program counter; some targets
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* will need to do more. If this hook is not implemented then the
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* default is to call @set_pc(tb->pc).
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* @handle_mmu_fault: Callback for handling an MMU fault.
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* @get_phys_page_debug: Callback for obtaining a physical address.
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* @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
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@ -172,11 +172,8 @@ int arm_set_cpu_on(struct uc_struct *uc,
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if (target_aa64) {
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target_cpu->env.xregs[0] = context_id;
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target_cpu->env.thumb = false;
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} else {
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target_cpu->env.regs[0] = context_id;
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target_cpu->env.thumb = entry & 1;
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entry &= 0xfffffffe;
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}
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/* Start the new CPU at the requested address */
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@ -34,8 +34,31 @@
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static void arm_cpu_set_pc(CPUState *cs, vaddr value)
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{
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ARMCPU *cpu = ARM_CPU(NULL, cs);
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CPUARMState *env = &cpu->env;
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cpu->env.regs[15] = value;
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if (is_a64(env)) {
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env->pc = value;
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env->thumb = 0;
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} else {
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env->regs[15] = value & ~1;
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env->thumb = value & 1;
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}
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}
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static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
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{
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ARMCPU *cpu = ARM_CPU(NULL, cs);
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CPUARMState *env = &cpu->env;
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/*
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* It's OK to look at env for the current mode here, because it's
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* never possible for an AArch64 TB to chain to an AArch32 TB.
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*/
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if (is_a64(env)) {
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env->pc = tb->pc;
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} else {
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env->regs[15] = tb->pc;
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}
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}
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static bool arm_cpu_has_work(CPUState *cs)
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@ -1781,6 +1804,7 @@ static void arm_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data
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cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
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//cc->dump_state = arm_cpu_dump_state;
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cc->set_pc = arm_cpu_set_pc;
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cc->synchronize_from_tb = arm_cpu_synchronize_from_tb;
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#ifdef CONFIG_USER_ONLY
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cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
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#else
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@ -337,26 +337,11 @@ static void aarch64_cpu_finalizefn(struct uc_struct *uc, Object *obj, void *opaq
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{
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}
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static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
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{
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ARMCPU *cpu = ARM_CPU(cs->uc, cs);
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/* It's OK to look at env for the current mode here, because it's
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* never possible for an AArch64 TB to chain to an AArch32 TB.
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* (Otherwise we would need to use synchronize_from_tb instead.)
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*/
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if (is_a64(&cpu->env)) {
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cpu->env.pc = value;
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} else {
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cpu->env.regs[15] = value;
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}
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}
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static void aarch64_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data)
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{
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CPUClass *cc = CPU_CLASS(uc, oc);
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cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
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cc->set_pc = aarch64_cpu_set_pc;
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}
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static void aarch64_cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)
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