arm: Clarify the logic of set_pc()

Until now, the set_pc logic was unclear, which raised questions about
whether it should be used directly, applying a value to PC or adding
additional checks, for example, set the Thumb bit in Arm cpu. Let's set
the set_pc logic for “Configure the PC, as was done in the ELF file”
and implement synchronize_with_tb hook for preserving PC to cpu_tb_exec.

Backports commit 42f6ed919325413392bea247a1e6f135deb469cd from qemu
This commit is contained in:
Julia Suvorova 2019-02-03 17:50:17 -05:00 committed by Lioncash
parent 50cf5634da
commit 93acc4dc56
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GPG key ID: 4E3C3CC1031BA9C7
4 changed files with 39 additions and 21 deletions

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@ -95,9 +95,21 @@ struct TranslationBlock;
* @get_arch_id: Callback for getting architecture-dependent CPU ID. * @get_arch_id: Callback for getting architecture-dependent CPU ID.
* @get_paging_enabled: Callback for inquiring whether paging is enabled. * @get_paging_enabled: Callback for inquiring whether paging is enabled.
* @get_memory_mapping: Callback for obtaining the memory mappings. * @get_memory_mapping: Callback for obtaining the memory mappings.
* @set_pc: Callback for setting the Program Counter register. * @set_pc: Callback for setting the Program Counter register. This
* should have the semantics used by the target architecture when
* setting the PC from a source such as an ELF file entry point;
* for example on Arm it will also set the Thumb mode bit based
* on the least significant bit of the new PC value.
* If the target behaviour here is anything other than "set
* the PC register to the value passed in" then the target must
* also implement the synchronize_from_tb hook.
* @synchronize_from_tb: Callback for synchronizing state from a TCG * @synchronize_from_tb: Callback for synchronizing state from a TCG
* #TranslationBlock. * #TranslationBlock. This is called when we abandon execution
* of a TB before starting it, and must set all parts of the CPU
* state which the previous TB in the chain may not have updated.
* This always includes at least the program counter; some targets
* will need to do more. If this hook is not implemented then the
* default is to call @set_pc(tb->pc).
* @handle_mmu_fault: Callback for handling an MMU fault. * @handle_mmu_fault: Callback for handling an MMU fault.
* @get_phys_page_debug: Callback for obtaining a physical address. * @get_phys_page_debug: Callback for obtaining a physical address.
* @get_phys_page_attrs_debug: Callback for obtaining a physical address and the * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the

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@ -172,11 +172,8 @@ int arm_set_cpu_on(struct uc_struct *uc,
if (target_aa64) { if (target_aa64) {
target_cpu->env.xregs[0] = context_id; target_cpu->env.xregs[0] = context_id;
target_cpu->env.thumb = false;
} else { } else {
target_cpu->env.regs[0] = context_id; target_cpu->env.regs[0] = context_id;
target_cpu->env.thumb = entry & 1;
entry &= 0xfffffffe;
} }
/* Start the new CPU at the requested address */ /* Start the new CPU at the requested address */

View file

@ -34,8 +34,31 @@
static void arm_cpu_set_pc(CPUState *cs, vaddr value) static void arm_cpu_set_pc(CPUState *cs, vaddr value)
{ {
ARMCPU *cpu = ARM_CPU(NULL, cs); ARMCPU *cpu = ARM_CPU(NULL, cs);
CPUARMState *env = &cpu->env;
cpu->env.regs[15] = value; if (is_a64(env)) {
env->pc = value;
env->thumb = 0;
} else {
env->regs[15] = value & ~1;
env->thumb = value & 1;
}
}
static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
{
ARMCPU *cpu = ARM_CPU(NULL, cs);
CPUARMState *env = &cpu->env;
/*
* It's OK to look at env for the current mode here, because it's
* never possible for an AArch64 TB to chain to an AArch32 TB.
*/
if (is_a64(env)) {
env->pc = tb->pc;
} else {
env->regs[15] = tb->pc;
}
} }
static bool arm_cpu_has_work(CPUState *cs) static bool arm_cpu_has_work(CPUState *cs)
@ -1781,6 +1804,7 @@ static void arm_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data
cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
//cc->dump_state = arm_cpu_dump_state; //cc->dump_state = arm_cpu_dump_state;
cc->set_pc = arm_cpu_set_pc; cc->set_pc = arm_cpu_set_pc;
cc->synchronize_from_tb = arm_cpu_synchronize_from_tb;
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY
cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
#else #else

View file

@ -337,26 +337,11 @@ static void aarch64_cpu_finalizefn(struct uc_struct *uc, Object *obj, void *opaq
{ {
} }
static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
{
ARMCPU *cpu = ARM_CPU(cs->uc, cs);
/* It's OK to look at env for the current mode here, because it's
* never possible for an AArch64 TB to chain to an AArch32 TB.
* (Otherwise we would need to use synchronize_from_tb instead.)
*/
if (is_a64(&cpu->env)) {
cpu->env.pc = value;
} else {
cpu->env.regs[15] = value;
}
}
static void aarch64_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data) static void aarch64_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data)
{ {
CPUClass *cc = CPU_CLASS(uc, oc); CPUClass *cc = CPU_CLASS(uc, oc);
cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->set_pc = aarch64_cpu_set_pc;
} }
static void aarch64_cpu_register(struct uc_struct *uc, const ARMCPUInfo *info) static void aarch64_cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)