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target/mips: Clean up handling of CP0 register 1

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Clean up handling of CP0 register 1

Backports commit 30deb4605bf0bb4cc0682216002dfed738bd5700 from qemu
This commit is contained in:
Aleksandar Markovic 2019-11-18 22:33:27 -05:00 committed by Lioncash
parent 47adeabf87
commit 9450b71a13
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 40 additions and 32 deletions
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8
qemu/target/mips/cpu.h
View file

@ -281,6 +281,14 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG00__MVPCONF1 3
#define CP0_REG00__VPCONTROL 4
/* CP0 Register 01 */
#define CP0_REG01__RANDOM 0
#define CP0_REG01__VPECONTROL 1
#define CP0_REG01__VPECONF0 2
#define CP0_REG01__VPECONF1 3
#define CP0_REG01__YQMASK 4
#define CP0_REG01__VPESCHEDULE 5
#define CP0_REG01__VPESCHEFBACK 6
#define CP0_REG01__VPEOPT 7
/* CP0 Register 02 */
#define CP0_REG02__ENTRYLO0 0
/* CP0 Register 03 */

64
qemu/target/mips/translate.c
View file

@ -6926,42 +6926,42 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
case 0:
case CP0_REG01__RANDOM:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
gen_helper_mfc0_random(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "Random";
break;
case 1:
case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_VPEControl));
register_name = "VPEControl";
break;
case 2:
case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_VPEConf0));
register_name = "VPEConf0";
break;
case 3:
case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_VPEConf1));
register_name = "VPEConf1";
break;
case 4:
case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(ctx, arg, offsetof(CPUMIPSState, CP0_YQMask));
register_name = "YQMask";
break;
case 5:
case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(ctx, arg, offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
case 6:
case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(ctx, arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
case 7:
case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_VPEOpt));
register_name = "VPEOpt";
@ -7683,43 +7683,43 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
case 0:
case CP0_REG01__RANDOM:
/* ignored */
register_name = "Random";
break;
case 1:
case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpecontrol(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "VPEControl";
break;
case 2:
case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf0(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "VPEConf0";
break;
case 3:
case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf1(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "VPEConf1";
break;
case 4:
case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_yqmask(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "YQMask";
break;
case 5:
case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
case 6:
case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
case 7:
case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeopt(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "VPEOpt";
@ -8424,42 +8424,42 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
case 0:
case CP0_REG01__RANDOM:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
gen_helper_mfc0_random(tcg_ctx, arg, tcg_ctx->cpu_env);
register_name = "Random";
break;
case 1:
case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_VPEControl));
register_name = "VPEControl";
break;
case 2:
case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_VPEConf0));
register_name = "VPEConf0";
break;
case 3:
case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_VPEConf1));
register_name = "VPEConf1";
break;
case 4:
case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
register_name = "YQMask";
break;
case 5:
case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
case 6:
case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
case 7:
case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_VPEOpt));
register_name = "VPEOpt";
@ -9136,41 +9136,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
case 0:
case CP0_REG01__RANDOM:
/* ignored */
register_name = "Random";
break;
case 1:
case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpecontrol(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "VPEControl";
break;
case 2:
case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf0(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "VPEConf0";
break;
case 3:
case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf1(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "VPEConf1";
break;
case 4:
case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_yqmask(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "YQMask";
break;
case 5:
case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
case 6:
case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
case 7:
case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeopt(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "VPEOpt";