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target/m68k: implement rtr instruction

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This is needed to boot MacOS ROM.

Pull the condition code and the program counter from the stack.

Operation:

(SP) -> CCR
SP + 2 -> SP
(SP) -> PC
SP + 4 -> SP

This operation is not privileged.

Backports 6abcec36741e589c855084e59195fc3454bf4be6
This commit is contained in:
Laurent Vivier 2021-03-12 14:28:21 -05:00 committed by Lioncash
parent c1ca2ae0ba
commit 945dd6fba9
1 changed files with 21 additions and 0 deletions
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21
qemu/target/m68k/translate.c
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@ -3074,6 +3074,26 @@ DISAS_INSN(rtd)
gen_jmp(s, tmp);
}
DISAS_INSN(rtr)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv tmp;
TCGv ccr;
TCGv sp;
sp = tcg_temp_new(tcg_ctx);
ccr = gen_load(s, OS_WORD, QREG_SP, 0, IS_USER(s));
tcg_gen_addi_i32(tcg_ctx, sp, QREG_SP, 2);
tmp = gen_load(s, OS_LONG, sp, 0, IS_USER(s));
tcg_gen_addi_i32(tcg_ctx, QREG_SP, sp, 4);
tcg_temp_free(tcg_ctx, sp);
gen_set_sr(s, ccr, true);
tcg_temp_free(tcg_ctx, ccr);
gen_jmp(s, tmp);
}
DISAS_INSN(rts)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
@ -6248,6 +6268,7 @@ void register_m68k_insns (CPUM68KState *env)
BASE(nop, 4e71, ffff);
INSN(rtd, 4e74, ffff, RTD);
BASE(rts, 4e75, ffff);
INSN(rtr, 4e77, ffff, M68000);
BASE(jump, 4e80, ffc0);
BASE(jump, 4ec0, ffc0);
INSN(addsubq, 5000, f080, M68000);