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target/m68k: add 680x0 "move to SR" instruction

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Some cleanup, and allows SR to be moved from any addressing mode.
Previous code was wrong for coldfire: coldfire also allows to
use addressing mode to set SR/CCR. It only supports Data register
to get SR/CCR (move from)

Backports commit b6a21d8d8f69ac04fd6180e752a65d582c07e948 from qemu
This commit is contained in:
Laurent Vivier 2018-03-06 08:33:47 -05:00 committed by Lioncash
parent 6559be21ad
commit 9527a5c994
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 25 additions and 16 deletions
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41
qemu/target/m68k/translate.c
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@ -2214,28 +2214,38 @@ static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_CC_N, val & CCF_N ? -1 : 0); tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_CC_N, val & CCF_N ? -1 : 0);
tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_CC_X, val & CCF_X ? 1 : 0); tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_CC_X, val & CCF_X ? 1 : 0);
} else { } else {
gen_helper_set_sr(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, val)); TCGv sr = tcg_const_i32(tcg_ctx, val);
gen_helper_set_sr(tcg_ctx, tcg_ctx->cpu_env, sr);
tcg_temp_free(tcg_ctx, sr);
} }
set_cc_op(s, CC_OP_FLAGS); set_cc_op(s, CC_OP_FLAGS);
} }
static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only)
int ccr_only)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
if ((insn & 0x38) == 0) {
if (ccr_only) { if (ccr_only) {
gen_helper_set_ccr(tcg_ctx, tcg_ctx->cpu_env, DREG(insn, 0)); gen_helper_set_ccr(tcg_ctx, tcg_ctx->cpu_env, val);
} else { } else {
gen_helper_set_sr(tcg_ctx, tcg_ctx->cpu_env, DREG(insn, 0)); gen_helper_set_sr(tcg_ctx, tcg_ctx->cpu_env, val);
} }
set_cc_op(s, CC_OP_FLAGS); set_cc_op(s, CC_OP_FLAGS);
} else if ((insn & 0x3f) == 0x3c) { }
static void gen_move_to_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
bool ccr_only)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if ((insn & 0x3f) == 0x3c) {
uint16_t val; uint16_t val;
val = read_im16(env, s); val = read_im16(env, s);
gen_set_sr_im(s, val, ccr_only); gen_set_sr_im(s, val, ccr_only);
} else { } else {
disas_undef(env, s, insn); TCGv src;
SRC_EA(env, src, OS_WORD, 0, NULL);
gen_set_sr(s, src, ccr_only);
} }
} }
@ -2632,7 +2642,7 @@ DISAS_INSN(neg)
DISAS_INSN(move_to_ccr) DISAS_INSN(move_to_ccr)
{ {
gen_set_sr(env, s, insn, 1); gen_move_to_sr(env, s, insn, true);
} }
DISAS_INSN(not) DISAS_INSN(not)
@ -4585,7 +4595,7 @@ DISAS_INSN(move_to_sr)
gen_exception(s, s->insn_pc, EXCP_PRIVILEGE); gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
return; return;
} }
gen_set_sr(env, s, insn, 0); gen_move_to_sr(env, s, insn, false);
gen_lookup_tb(s); gen_lookup_tb(s);
} }
@ -5770,9 +5780,8 @@ void register_m68k_insns (CPUM68KState *env)
BASE(move_to_ccr, 44c0, ffc0); BASE(move_to_ccr, 44c0, ffc0);
INSN(not, 4680, fff8, CF_ISA_A); INSN(not, 4680, fff8, CF_ISA_A);
INSN(not, 4600, ff00, M68000); INSN(not, 4600, ff00, M68000);
INSN(undef, 46c0, ffc0, M68000);
#if defined(CONFIG_SOFTMMU) #if defined(CONFIG_SOFTMMU)
INSN(move_to_sr, 46c0, ffc0, CF_ISA_A); BASE(move_to_sr, 46c0, ffc0);
#endif #endif
INSN(nbcd, 4800, ffc0, M68000); INSN(nbcd, 4800, ffc0, M68000);
INSN(linkl, 4808, fff8, M68000); INSN(linkl, 4808, fff8, M68000);