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target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode

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while IMMU/DMMU is disabled
- ignore MMU-faults in hypervisorv mode or if CPU doesn't have hypervisor
- signal TT_INSN_REAL_TRANSLATION_MISS/TT_DATA_REAL_TRANSLATION_MISS otherwise

Backports commit 1ceca928538a3633b74a7dc718a05ce6767f2f76 from qemu
This commit is contained in:
Artyom Tarasenko 2018-03-01 20:25:20 -05:00 committed by Lioncash
parent d905278b86
commit 96af2cfb58
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 15 additions and 2 deletions
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2
qemu/target-sparc/cpu.h
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@ -69,6 +69,8 @@
#define TT_DATA_ACCESS 0x32 #define TT_DATA_ACCESS 0x32
#define TT_UNALIGNED 0x34 #define TT_UNALIGNED 0x34
#define TT_PRIV_ACT 0x37 #define TT_PRIV_ACT 0x37
#define TT_INSN_REAL_TRANSLATION_MISS 0x3e
#define TT_DATA_REAL_TRANSLATION_MISS 0x3f
#define TT_EXTINT 0x40 #define TT_EXTINT 0x40
#define TT_IVEC 0x60 #define TT_IVEC 0x60
#define TT_TMISS 0x64 #define TT_TMISS 0x64

15
qemu/target-sparc/ldst_helper.c
View file

@ -1675,14 +1675,25 @@ void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
{ {
SPARCCPU *cpu = SPARC_CPU(cs->uc, cs); SPARCCPU *cpu = SPARC_CPU(cs->uc, cs);
CPUSPARCState *env = &cpu->env; CPUSPARCState *env = &cpu->env;
int tt = is_exec ? TT_CODE_ACCESS : TT_DATA_ACCESS;
#ifdef DEBUG_UNASSIGNED #ifdef DEBUG_UNASSIGNED
printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
"\n", addr, env->pc); "\n", addr, env->pc);
#endif #endif
cpu_raise_exception_ra(env, tt, GETPC()); if (is_exec) { /* XXX has_hypervisor */
if (env->lsu & (IMMU_E)) {
cpu_raise_exception_ra(env, TT_CODE_ACCESS, GETPC());
} else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) {
cpu_raise_exception_ra(env, TT_INSN_REAL_TRANSLATION_MISS, GETPC());
}
} else {
if (env->lsu & (DMMU_E)) {
cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC());
} else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) {
cpu_raise_exception_ra(env, TT_DATA_REAL_TRANSLATION_MISS, GETPC());
}
}
} }
#endif #endif
#endif #endif