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target-m68k: add addressing modes to scc
Backports commit d5a3cf33f2f65069d2f79a6e349f0d8140f02bb4 from qemu
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77b1754376
commit
977c3fe6c4
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@ -1003,27 +1003,6 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
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free_cond(s, &c);
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}
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DISAS_INSN(scc)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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DisasCompare c;
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int cond;
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TCGv reg, tmp;
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cond = (insn >> 8) & 0xf;
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gen_cc_cond(&c, s, cond);
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tmp = tcg_temp_new(tcg_ctx);
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tcg_gen_setcond_i32(tcg_ctx, c.tcond, tmp, c.v1, c.v2);
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free_cond(s, &c);
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cond = (insn >> 8) & 0xf;
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reg = DREG(insn, 0);
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tcg_gen_neg_i32(tcg_ctx, tmp, tmp);
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tcg_gen_deposit_i32(tcg_ctx, reg, reg, tmp, 0, 8);
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tcg_temp_free(tcg_ctx, tmp);
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}
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/* Force a TB lookup after an instruction that changes the CPU state. */
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static void gen_lookup_tb(DisasContext *s)
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{
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@ -1109,6 +1088,25 @@ static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
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s->is_jmp = DISAS_TB_JUMP;
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}
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DISAS_INSN(scc)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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DisasCompare c;
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int cond;
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TCGv tmp;
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cond = (insn >> 8) & 0xf;
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gen_cc_cond(&c, s, cond);
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tmp = tcg_temp_new(tcg_ctx);
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tcg_gen_setcond_i32(tcg_ctx, c.tcond, tmp, c.v1, c.v2);
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free_cond(s, &c);
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tcg_gen_neg_i32(tcg_ctx, tmp, tmp);
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DEST_EA(env, insn, OS_BYTE, tmp, NULL);
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tcg_temp_free(tcg_ctx, tmp);
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}
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DISAS_INSN(undef_mac)
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{
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gen_exception(s, s->pc - 2, EXCP_LINEA);
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@ -3219,7 +3217,8 @@ void register_m68k_insns (CPUM68KState *env)
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INSN(jump, 4ec0, ffc0, M68000);
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INSN(addsubq, 5000, f080, M68000);
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INSN(addsubq, 5080, f0c0, M68000);
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INSN(scc, 50c0, f0f8, CF_ISA_A);
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INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */
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INSN(scc, 50c0, f0c0, M68000); /* Scc.B <EA> */
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INSN(addsubq, 5080, f1c0, CF_ISA_A);
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INSN(tpf, 51f8, fff8, CF_ISA_A);
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