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target-m68k: add addressing modes to scc

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Backports commit d5a3cf33f2f65069d2f79a6e349f0d8140f02bb4 from qemu
This commit is contained in:
Laurent Vivier 2018-02-28 00:42:53 -05:00 committed by Lioncash
parent 77b1754376
commit 977c3fe6c4
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 21 additions and 22 deletions
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43
qemu/target-m68k/translate.c
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@ -1003,27 +1003,6 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
free_cond(s, &c); free_cond(s, &c);
} }
DISAS_INSN(scc)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
DisasCompare c;
int cond;
TCGv reg, tmp;
cond = (insn >> 8) & 0xf;
gen_cc_cond(&c, s, cond);
tmp = tcg_temp_new(tcg_ctx);
tcg_gen_setcond_i32(tcg_ctx, c.tcond, tmp, c.v1, c.v2);
free_cond(s, &c);
cond = (insn >> 8) & 0xf;
reg = DREG(insn, 0);
tcg_gen_neg_i32(tcg_ctx, tmp, tmp);
tcg_gen_deposit_i32(tcg_ctx, reg, reg, tmp, 0, 8);
tcg_temp_free(tcg_ctx, tmp);
}
/* Force a TB lookup after an instruction that changes the CPU state. */ /* Force a TB lookup after an instruction that changes the CPU state. */
static void gen_lookup_tb(DisasContext *s) static void gen_lookup_tb(DisasContext *s)
{ {
@ -1109,6 +1088,25 @@ static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
s->is_jmp = DISAS_TB_JUMP; s->is_jmp = DISAS_TB_JUMP;
} }
DISAS_INSN(scc)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
DisasCompare c;
int cond;
TCGv tmp;
cond = (insn >> 8) & 0xf;
gen_cc_cond(&c, s, cond);
tmp = tcg_temp_new(tcg_ctx);
tcg_gen_setcond_i32(tcg_ctx, c.tcond, tmp, c.v1, c.v2);
free_cond(s, &c);
tcg_gen_neg_i32(tcg_ctx, tmp, tmp);
DEST_EA(env, insn, OS_BYTE, tmp, NULL);
tcg_temp_free(tcg_ctx, tmp);
}
DISAS_INSN(undef_mac) DISAS_INSN(undef_mac)
{ {
gen_exception(s, s->pc - 2, EXCP_LINEA); gen_exception(s, s->pc - 2, EXCP_LINEA);
@ -3219,7 +3217,8 @@ void register_m68k_insns (CPUM68KState *env)
INSN(jump, 4ec0, ffc0, M68000); INSN(jump, 4ec0, ffc0, M68000);
INSN(addsubq, 5000, f080, M68000); INSN(addsubq, 5000, f080, M68000);
INSN(addsubq, 5080, f0c0, M68000); INSN(addsubq, 5080, f0c0, M68000);
INSN(scc, 50c0, f0f8, CF_ISA_A); INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */
INSN(scc, 50c0, f0c0, M68000); /* Scc.B <EA> */
INSN(addsubq, 5080, f1c0, CF_ISA_A); INSN(addsubq, 5080, f1c0, CF_ISA_A);
INSN(tpf, 51f8, fff8, CF_ISA_A); INSN(tpf, 51f8, fff8, CF_ISA_A);