mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-03-23 02:55:06 +00:00
target/arm: Make sure M-profile FPSCR RES0 bits are not settable
Enforce that for M-profile various FPSCR bits which are RES0 there but have defined meanings on A-profile are never settable. This ensures that M-profile code can't enable the A-profile behaviour (notably vector length/stride handling) by accident. Backports commit 5bcf8ed9401e62c73158ba110864ee1375558bf7 from qemu
This commit is contained in:
parent
7f59d62f4a
commit
978cd9c524
|
@ -105,6 +105,14 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
|
|||
val &= ~FPCR_FZ16;
|
||||
}
|
||||
|
||||
if (arm_feature(env, ARM_FEATURE_M)) {
|
||||
/*
|
||||
* M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
|
||||
* and also for the trapped-exception-handling bits IxE.
|
||||
*/
|
||||
val &= 0xf7c0009f;
|
||||
}
|
||||
|
||||
/*
|
||||
* We don't implement trapped exception handling, so the
|
||||
* trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
|
||||
|
|
Loading…
Reference in a new issue