target/riscv: vector single-width integer multiply instructions

qemu/header_gen.py

@@ -6442,6 +6442,38 @@ riscv_symbols = (
     'helper_vmax_vx_h',
     'helper_vmax_vx_w',
     'helper_vmax_vx_d',
+    'helper_vmul_vv_b',
+    'helper_vmul_vv_h',
+    'helper_vmul_vv_w',
+    'helper_vmul_vv_d',
+    'helper_vmulh_vv_b',
+    'helper_vmulh_vv_h',
+    'helper_vmulh_vv_w',
+    'helper_vmulh_vv_d',
+    'helper_vmulhu_vv_b',
+    'helper_vmulhu_vv_h',
+    'helper_vmulhu_vv_w',
+    'helper_vmulhu_vv_d',
+    'helper_vmulhsu_vv_b',
+    'helper_vmulhsu_vv_h',
+    'helper_vmulhsu_vv_w',
+    'helper_vmulhsu_vv_d',
+    'helper_vmul_vx_b',
+    'helper_vmul_vx_h',
+    'helper_vmul_vx_w',
+    'helper_vmul_vx_d',
+    'helper_vmulh_vx_b',
+    'helper_vmulh_vx_h',
+    'helper_vmulh_vx_w',
+    'helper_vmulh_vx_d',
+    'helper_vmulhu_vx_b',
+    'helper_vmulhu_vx_h',
+    'helper_vmulhu_vx_w',
+    'helper_vmulhu_vx_d',
+    'helper_vmulhsu_vx_b',
+    'helper_vmulhsu_vx_h',
+    'helper_vmulhsu_vx_w',
+    'helper_vmulhsu_vx_d',
     'helper_vmseq_vv_b',
     'helper_vmseq_vv_h',
     'helper_vmseq_vv_w',

qemu/riscv32.h

@@ -3896,6 +3896,38 @@
 #define helper_vmax_vx_h helper_vmax_vx_h_riscv32
 #define helper_vmax_vx_w helper_vmax_vx_w_riscv32
 #define helper_vmax_vx_d helper_vmax_vx_d_riscv32
+#define helper_vmul_vv_b helper_vmul_vv_b_riscv32
+#define helper_vmul_vv_h helper_vmul_vv_h_riscv32
+#define helper_vmul_vv_w helper_vmul_vv_w_riscv32
+#define helper_vmul_vv_d helper_vmul_vv_d_riscv32
+#define helper_vmulh_vv_b helper_vmulh_vv_b_riscv32
+#define helper_vmulh_vv_h helper_vmulh_vv_h_riscv32
+#define helper_vmulh_vv_w helper_vmulh_vv_w_riscv32
+#define helper_vmulh_vv_d helper_vmulh_vv_d_riscv32
+#define helper_vmulhu_vv_b helper_vmulhu_vv_b_riscv32
+#define helper_vmulhu_vv_h helper_vmulhu_vv_h_riscv32
+#define helper_vmulhu_vv_w helper_vmulhu_vv_w_riscv32
+#define helper_vmulhu_vv_d helper_vmulhu_vv_d_riscv32
+#define helper_vmulhsu_vv_b helper_vmulhsu_vv_b_riscv32
+#define helper_vmulhsu_vv_h helper_vmulhsu_vv_h_riscv32
+#define helper_vmulhsu_vv_w helper_vmulhsu_vv_w_riscv32
+#define helper_vmulhsu_vv_d helper_vmulhsu_vv_d_riscv32
+#define helper_vmul_vx_b helper_vmul_vx_b_riscv32
+#define helper_vmul_vx_h helper_vmul_vx_h_riscv32
+#define helper_vmul_vx_w helper_vmul_vx_w_riscv32
+#define helper_vmul_vx_d helper_vmul_vx_d_riscv32
+#define helper_vmulh_vx_b helper_vmulh_vx_b_riscv32
+#define helper_vmulh_vx_h helper_vmulh_vx_h_riscv32
+#define helper_vmulh_vx_w helper_vmulh_vx_w_riscv32
+#define helper_vmulh_vx_d helper_vmulh_vx_d_riscv32
+#define helper_vmulhu_vx_b helper_vmulhu_vx_b_riscv32
+#define helper_vmulhu_vx_h helper_vmulhu_vx_h_riscv32
+#define helper_vmulhu_vx_w helper_vmulhu_vx_w_riscv32
+#define helper_vmulhu_vx_d helper_vmulhu_vx_d_riscv32
+#define helper_vmulhsu_vx_b helper_vmulhsu_vx_b_riscv32
+#define helper_vmulhsu_vx_h helper_vmulhsu_vx_h_riscv32
+#define helper_vmulhsu_vx_w helper_vmulhsu_vx_w_riscv32
+#define helper_vmulhsu_vx_d helper_vmulhsu_vx_d_riscv32
 #define helper_vmseq_vv_b helper_vmseq_vv_b_riscv32
 #define helper_vmseq_vv_h helper_vmseq_vv_h_riscv32
 #define helper_vmseq_vv_w helper_vmseq_vv_w_riscv32

qemu/riscv64.h

@@ -3896,6 +3896,38 @@
 #define helper_vmax_vx_h helper_vmax_vx_h_riscv64
 #define helper_vmax_vx_w helper_vmax_vx_w_riscv64
 #define helper_vmax_vx_d helper_vmax_vx_d_riscv64
+#define helper_vmul_vv_b helper_vmul_vv_b_riscv64
+#define helper_vmul_vv_h helper_vmul_vv_h_riscv64
+#define helper_vmul_vv_w helper_vmul_vv_w_riscv64
+#define helper_vmul_vv_d helper_vmul_vv_d_riscv64
+#define helper_vmulh_vv_b helper_vmulh_vv_b_riscv64
+#define helper_vmulh_vv_h helper_vmulh_vv_h_riscv64
+#define helper_vmulh_vv_w helper_vmulh_vv_w_riscv64
+#define helper_vmulh_vv_d helper_vmulh_vv_d_riscv64
+#define helper_vmulhu_vv_b helper_vmulhu_vv_b_riscv64
+#define helper_vmulhu_vv_h helper_vmulhu_vv_h_riscv64
+#define helper_vmulhu_vv_w helper_vmulhu_vv_w_riscv64
+#define helper_vmulhu_vv_d helper_vmulhu_vv_d_riscv64
+#define helper_vmulhsu_vv_b helper_vmulhsu_vv_b_riscv64
+#define helper_vmulhsu_vv_h helper_vmulhsu_vv_h_riscv64
+#define helper_vmulhsu_vv_w helper_vmulhsu_vv_w_riscv64
+#define helper_vmulhsu_vv_d helper_vmulhsu_vv_d_riscv64
+#define helper_vmul_vx_b helper_vmul_vx_b_riscv64
+#define helper_vmul_vx_h helper_vmul_vx_h_riscv64
+#define helper_vmul_vx_w helper_vmul_vx_w_riscv64
+#define helper_vmul_vx_d helper_vmul_vx_d_riscv64
+#define helper_vmulh_vx_b helper_vmulh_vx_b_riscv64
+#define helper_vmulh_vx_h helper_vmulh_vx_h_riscv64
+#define helper_vmulh_vx_w helper_vmulh_vx_w_riscv64
+#define helper_vmulh_vx_d helper_vmulh_vx_d_riscv64
+#define helper_vmulhu_vx_b helper_vmulhu_vx_b_riscv64
+#define helper_vmulhu_vx_h helper_vmulhu_vx_h_riscv64
+#define helper_vmulhu_vx_w helper_vmulhu_vx_w_riscv64
+#define helper_vmulhu_vx_d helper_vmulhu_vx_d_riscv64
+#define helper_vmulhsu_vx_b helper_vmulhsu_vx_b_riscv64
+#define helper_vmulhsu_vx_h helper_vmulhsu_vx_h_riscv64
+#define helper_vmulhsu_vx_w helper_vmulhsu_vx_w_riscv64
+#define helper_vmulhsu_vx_d helper_vmulhsu_vx_d_riscv64
 #define helper_vmseq_vv_b helper_vmseq_vv_b_riscv64
 #define helper_vmseq_vv_h helper_vmseq_vv_h_riscv64
 #define helper_vmseq_vv_w helper_vmseq_vv_w_riscv64

qemu/target/riscv/helper.h

@@ -525,3 +525,36 @@ DEF_HELPER_6(vmax_vx_b, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vmax_vx_h, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vmax_vx_w, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vmax_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmul_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulh_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulh_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulh_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulh_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulhu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulhu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulhu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulhu_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulhsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulhsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulhsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulhsu_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmul_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmul_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmul_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmul_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulh_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulh_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulh_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulh_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulhu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulhu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulhu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulhu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulhsu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulhsu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulhsu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulhsu_vx_d, void, ptr, ptr, tl, ptr, env, i32)

qemu/target/riscv/insn32.decode

@@ -359,6 +359,14 @@ vmaxu_vv        000110 . ..... ..... 000 ..... 1010111 @r_vm
 vmaxu_vx        000110 . ..... ..... 100 ..... 1010111 @r_vm
 vmax_vv         000111 . ..... ..... 000 ..... 1010111 @r_vm
 vmax_vx         000111 . ..... ..... 100 ..... 1010111 @r_vm
+vmul_vv         100101 . ..... ..... 010 ..... 1010111 @r_vm
+vmul_vx         100101 . ..... ..... 110 ..... 1010111 @r_vm
+vmulh_vv        100111 . ..... ..... 010 ..... 1010111 @r_vm
+vmulh_vx        100111 . ..... ..... 110 ..... 1010111 @r_vm
+vmulhu_vv       100100 . ..... ..... 010 ..... 1010111 @r_vm
+vmulhu_vx       100100 . ..... ..... 110 ..... 1010111 @r_vm
+vmulhsu_vv      100110 . ..... ..... 010 ..... 1010111 @r_vm
+vmulhsu_vx      100110 . ..... ..... 110 ..... 1010111 @r_vm
 
 vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm
 vsetvl          1000000 ..... ..... 111 ..... 1010111  @r

qemu/target/riscv/insn_trans/trans_rvv.inc.c

@@ -1502,3 +1502,13 @@ GEN_OPIVX_TRANS(vminu_vx, opivx_check)
 GEN_OPIVX_TRANS(vmin_vx,  opivx_check)
 GEN_OPIVX_TRANS(vmaxu_vx, opivx_check)
 GEN_OPIVX_TRANS(vmax_vx,  opivx_check)
+
+/* Vector Single-Width Integer Multiply Instructions */
+GEN_OPIVV_GVEC_TRANS(vmul_vv,  mul)
+GEN_OPIVV_TRANS(vmulh_vv, opivv_check)
+GEN_OPIVV_TRANS(vmulhu_vv, opivv_check)
+GEN_OPIVV_TRANS(vmulhsu_vv, opivv_check)
+GEN_OPIVX_GVEC_TRANS(vmul_vx,  muls)
+GEN_OPIVX_TRANS(vmulh_vx, opivx_check)
+GEN_OPIVX_TRANS(vmulhu_vx, opivx_check)
+GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check)

qemu/target/riscv/vector_helper.c

@@ -860,6 +860,10 @@ GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl)
 #define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t
 #define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t
 #define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t
+#define OP_SUS_B int8_t, uint8_t, int8_t, uint8_t, int8_t
+#define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t
+#define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t
+#define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t
 
 /* operation of two vector elements */
 typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
@@ -1590,3 +1594,162 @@ GEN_VEXT_VX(vmax_vx_b, 1, 1, clearb)
 GEN_VEXT_VX(vmax_vx_h, 2, 2, clearh)
 GEN_VEXT_VX(vmax_vx_w, 4, 4, clearl)
 GEN_VEXT_VX(vmax_vx_d, 8, 8, clearq)
+
+/* Vector Single-Width Integer Multiply Instructions */
+#define DO_MUL(N, M) (N * M)
+RVVCALL(OPIVV2, vmul_vv_b, OP_SSS_B, H1, H1, H1, DO_MUL)
+RVVCALL(OPIVV2, vmul_vv_h, OP_SSS_H, H2, H2, H2, DO_MUL)
+RVVCALL(OPIVV2, vmul_vv_w, OP_SSS_W, H4, H4, H4, DO_MUL)
+RVVCALL(OPIVV2, vmul_vv_d, OP_SSS_D, H8, H8, H8, DO_MUL)
+GEN_VEXT_VV(vmul_vv_b, 1, 1, clearb)
+GEN_VEXT_VV(vmul_vv_h, 2, 2, clearh)
+GEN_VEXT_VV(vmul_vv_w, 4, 4, clearl)
+GEN_VEXT_VV(vmul_vv_d, 8, 8, clearq)
+
+static int8_t do_mulh_b(int8_t s2, int8_t s1)
+{
+    return (int16_t)s2 * (int16_t)s1 >> 8;
+}
+
+static int16_t do_mulh_h(int16_t s2, int16_t s1)
+{
+    return (int32_t)s2 * (int32_t)s1 >> 16;
+}
+
+static int32_t do_mulh_w(int32_t s2, int32_t s1)
+{
+    return (int64_t)s2 * (int64_t)s1 >> 32;
+}
+
+static int64_t do_mulh_d(int64_t s2, int64_t s1)
+{
+    uint64_t hi_64, lo_64;
+
+    muls64(&lo_64, &hi_64, s1, s2);
+    return hi_64;
+}
+
+static uint8_t do_mulhu_b(uint8_t s2, uint8_t s1)
+{
+    return (uint16_t)s2 * (uint16_t)s1 >> 8;
+}
+
+static uint16_t do_mulhu_h(uint16_t s2, uint16_t s1)
+{
+    return (uint32_t)s2 * (uint32_t)s1 >> 16;
+}
+
+static uint32_t do_mulhu_w(uint32_t s2, uint32_t s1)
+{
+    return (uint64_t)s2 * (uint64_t)s1 >> 32;
+}
+
+static uint64_t do_mulhu_d(uint64_t s2, uint64_t s1)
+{
+    uint64_t hi_64, lo_64;
+
+    mulu64(&lo_64, &hi_64, s2, s1);
+    return hi_64;
+}
+
+static int8_t do_mulhsu_b(int8_t s2, uint8_t s1)
+{
+    return (int16_t)s2 * (uint16_t)s1 >> 8;
+}
+
+static int16_t do_mulhsu_h(int16_t s2, uint16_t s1)
+{
+    return (int32_t)s2 * (uint32_t)s1 >> 16;
+}
+
+static int32_t do_mulhsu_w(int32_t s2, uint32_t s1)
+{
+    return (int64_t)s2 * (uint64_t)s1 >> 32;
+}
+
+/*
+ * Let  A = signed operand,
+ *      B = unsigned operand
+ *      P = mulu64(A, B), unsigned product
+ *
+ * LET  X = 2 ** 64  - A, 2's complement of A
+ *      SP = signed product
+ * THEN
+ *      IF A < 0
+ *          SP = -X * B
+ *             = -(2 ** 64 - A) * B
+ *             = A * B - 2 ** 64 * B
+ *             = P - 2 ** 64 * B
+ *      ELSE
+ *          SP = P
+ * THEN
+ *      HI_P -= (A < 0 ? B : 0)
+ */
+
+static int64_t do_mulhsu_d(int64_t s2, uint64_t s1)
+{
+    uint64_t hi_64, lo_64;
+
+    mulu64(&lo_64, &hi_64, s2, s1);
+
+    hi_64 -= s2 < 0 ? s1 : 0;
+    return hi_64;
+}
+
+RVVCALL(OPIVV2, vmulh_vv_b, OP_SSS_B, H1, H1, H1, do_mulh_b)
+RVVCALL(OPIVV2, vmulh_vv_h, OP_SSS_H, H2, H2, H2, do_mulh_h)
+RVVCALL(OPIVV2, vmulh_vv_w, OP_SSS_W, H4, H4, H4, do_mulh_w)
+RVVCALL(OPIVV2, vmulh_vv_d, OP_SSS_D, H8, H8, H8, do_mulh_d)
+RVVCALL(OPIVV2, vmulhu_vv_b, OP_UUU_B, H1, H1, H1, do_mulhu_b)
+RVVCALL(OPIVV2, vmulhu_vv_h, OP_UUU_H, H2, H2, H2, do_mulhu_h)
+RVVCALL(OPIVV2, vmulhu_vv_w, OP_UUU_W, H4, H4, H4, do_mulhu_w)
+RVVCALL(OPIVV2, vmulhu_vv_d, OP_UUU_D, H8, H8, H8, do_mulhu_d)
+RVVCALL(OPIVV2, vmulhsu_vv_b, OP_SUS_B, H1, H1, H1, do_mulhsu_b)
+RVVCALL(OPIVV2, vmulhsu_vv_h, OP_SUS_H, H2, H2, H2, do_mulhsu_h)
+RVVCALL(OPIVV2, vmulhsu_vv_w, OP_SUS_W, H4, H4, H4, do_mulhsu_w)
+RVVCALL(OPIVV2, vmulhsu_vv_d, OP_SUS_D, H8, H8, H8, do_mulhsu_d)
+GEN_VEXT_VV(vmulh_vv_b, 1, 1, clearb)
+GEN_VEXT_VV(vmulh_vv_h, 2, 2, clearh)
+GEN_VEXT_VV(vmulh_vv_w, 4, 4, clearl)
+GEN_VEXT_VV(vmulh_vv_d, 8, 8, clearq)
+GEN_VEXT_VV(vmulhu_vv_b, 1, 1, clearb)
+GEN_VEXT_VV(vmulhu_vv_h, 2, 2, clearh)
+GEN_VEXT_VV(vmulhu_vv_w, 4, 4, clearl)
+GEN_VEXT_VV(vmulhu_vv_d, 8, 8, clearq)
+GEN_VEXT_VV(vmulhsu_vv_b, 1, 1, clearb)
+GEN_VEXT_VV(vmulhsu_vv_h, 2, 2, clearh)
+GEN_VEXT_VV(vmulhsu_vv_w, 4, 4, clearl)
+GEN_VEXT_VV(vmulhsu_vv_d, 8, 8, clearq)
+
+RVVCALL(OPIVX2, vmul_vx_b, OP_SSS_B, H1, H1, DO_MUL)
+RVVCALL(OPIVX2, vmul_vx_h, OP_SSS_H, H2, H2, DO_MUL)
+RVVCALL(OPIVX2, vmul_vx_w, OP_SSS_W, H4, H4, DO_MUL)
+RVVCALL(OPIVX2, vmul_vx_d, OP_SSS_D, H8, H8, DO_MUL)
+RVVCALL(OPIVX2, vmulh_vx_b, OP_SSS_B, H1, H1, do_mulh_b)
+RVVCALL(OPIVX2, vmulh_vx_h, OP_SSS_H, H2, H2, do_mulh_h)
+RVVCALL(OPIVX2, vmulh_vx_w, OP_SSS_W, H4, H4, do_mulh_w)
+RVVCALL(OPIVX2, vmulh_vx_d, OP_SSS_D, H8, H8, do_mulh_d)
+RVVCALL(OPIVX2, vmulhu_vx_b, OP_UUU_B, H1, H1, do_mulhu_b)
+RVVCALL(OPIVX2, vmulhu_vx_h, OP_UUU_H, H2, H2, do_mulhu_h)
+RVVCALL(OPIVX2, vmulhu_vx_w, OP_UUU_W, H4, H4, do_mulhu_w)
+RVVCALL(OPIVX2, vmulhu_vx_d, OP_UUU_D, H8, H8, do_mulhu_d)
+RVVCALL(OPIVX2, vmulhsu_vx_b, OP_SUS_B, H1, H1, do_mulhsu_b)
+RVVCALL(OPIVX2, vmulhsu_vx_h, OP_SUS_H, H2, H2, do_mulhsu_h)
+RVVCALL(OPIVX2, vmulhsu_vx_w, OP_SUS_W, H4, H4, do_mulhsu_w)
+RVVCALL(OPIVX2, vmulhsu_vx_d, OP_SUS_D, H8, H8, do_mulhsu_d)
+GEN_VEXT_VX(vmul_vx_b, 1, 1, clearb)
+GEN_VEXT_VX(vmul_vx_h, 2, 2, clearh)
+GEN_VEXT_VX(vmul_vx_w, 4, 4, clearl)
+GEN_VEXT_VX(vmul_vx_d, 8, 8, clearq)
+GEN_VEXT_VX(vmulh_vx_b, 1, 1, clearb)
+GEN_VEXT_VX(vmulh_vx_h, 2, 2, clearh)
+GEN_VEXT_VX(vmulh_vx_w, 4, 4, clearl)
+GEN_VEXT_VX(vmulh_vx_d, 8, 8, clearq)
+GEN_VEXT_VX(vmulhu_vx_b, 1, 1, clearb)
+GEN_VEXT_VX(vmulhu_vx_h, 2, 2, clearh)
+GEN_VEXT_VX(vmulhu_vx_w, 4, 4, clearl)
+GEN_VEXT_VX(vmulhu_vx_d, 8, 8, clearq)
+GEN_VEXT_VX(vmulhsu_vx_b, 1, 1, clearb)
+GEN_VEXT_VX(vmulhsu_vx_h, 2, 2, clearh)
+GEN_VEXT_VX(vmulhsu_vx_w, 4, 4, clearl)
+GEN_VEXT_VX(vmulhsu_vx_d, 8, 8, clearq)