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target-arm: Don't permit ARMv8-only Neon insns on ARMv7
The Neon instructions VCVTA, VCVTM, VCVTN, VCVTP, VRINTA, VRINTM, VRINTN, VRINTP, VRINTX, and VRINTZ were only introduced with ARMv8, so they need a guard to make them UNDEF if the CPU only supports ARMv7. (We got this right for all the other new-in-v8 insns, but forgot it for these Neon 2-reg-misc ops.) Backports commit fe8fcf3d642b4de1369841bf6acac13e0ec8770d from qemu
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@ -5454,6 +5454,30 @@ static int neon_2rm_is_float_op(int op)
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op >= NEON_2RM_VRECPE_F);
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}
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static bool neon_2rm_is_v8_op(int op)
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{
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/* Return true if this neon 2reg-misc op is ARMv8 and up */
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switch (op) {
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case NEON_2RM_VRINTN:
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case NEON_2RM_VRINTA:
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case NEON_2RM_VRINTM:
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case NEON_2RM_VRINTP:
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case NEON_2RM_VRINTZ:
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case NEON_2RM_VRINTX:
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case NEON_2RM_VCVTAU:
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case NEON_2RM_VCVTAS:
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case NEON_2RM_VCVTNU:
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case NEON_2RM_VCVTNS:
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case NEON_2RM_VCVTPU:
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case NEON_2RM_VCVTPS:
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case NEON_2RM_VCVTMU:
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case NEON_2RM_VCVTMS:
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return true;
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default:
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return false;
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}
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}
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/* Each entry in this array has bit n set if the insn allows
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* size value n (otherwise it will UNDEF). Since unallocated
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* op values will have no bits set they always UNDEF.
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@ -6944,6 +6968,10 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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if ((neon_2rm_sizes[op] & (1 << size)) == 0) {
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return 1;
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}
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if (neon_2rm_is_v8_op(op) &&
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!arm_dc_feature(s, ARM_FEATURE_V8)) {
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return 1;
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}
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if ((op != NEON_2RM_VMOVN && op != NEON_2RM_VQMOVN) &&
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q && ((rm | rd) & 1)) {
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return 1;
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