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target/mips: realign comments to fix checkpatch warnings

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Realign comments to fix warnings issued by checkpatc.pl tool
"WARNING: Block comments use a leading /* on a separate line"
within "target/mips/cpu.h" file.

Backports commit 9e72f33d854b0a817c0d2fe4bca693b76f0fe776 from qemu
This commit is contained in:
Jules Irenge 2019-05-28 19:49:57 -04:00 committed by Lioncash
parent cf39970750
commit 9c7f2f2e78
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 22 additions and 12 deletions
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34
qemu/target/mips/cpu.h
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@ -36,7 +36,8 @@ union fpr_t {
/* FPU/MSA register mapping is not tested on big-endian hosts. */ /* FPU/MSA register mapping is not tested on big-endian hosts. */
wr_t wr; /* vector data */ wr_t wr; /* vector data */
}; };
/* define FP_ENDIAN_IDX to access the same location /*
*define FP_ENDIAN_IDX to access the same location
* in the fpr_t union regardless of the host endianness * in the fpr_t union regardless of the host endianness
*/ */
#if defined(HOST_WORDS_BIGENDIAN) #if defined(HOST_WORDS_BIGENDIAN)
@ -972,9 +973,11 @@ struct CPUMIPSState {
/* TMASK defines different execution modes */ /* TMASK defines different execution modes */
#define MIPS_HFLAG_TMASK 0x1F5807FF #define MIPS_HFLAG_TMASK 0x1F5807FF
#define MIPS_HFLAG_MODE 0x00007 /* execution modes */ #define MIPS_HFLAG_MODE 0x00007 /* execution modes */
/* The KSU flags must be the lowest bits in hflags. The flag order /*
must be the same as defined for CP0 Status. This allows to use * The KSU flags must be the lowest bits in hflags. The flag order
the bits as the value of mmu_idx. */ * must be the same as defined for CP0 Status. This allows to use
* the bits as the value of mmu_idx.
*/
#define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */
#define MIPS_HFLAG_UM 0x00002 /* user mode flag */ #define MIPS_HFLAG_UM 0x00002 /* user mode flag */
#define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */
@ -984,18 +987,22 @@ struct CPUMIPSState {
#define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */
#define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */
#define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */
/* True if the MIPS IV COP1X instructions can be used. This also /*
controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S * True if the MIPS IV COP1X instructions can be used. This also
and RSQRT.D. */ * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
* and RSQRT.D.
*/
#define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */
#define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */
#define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */ #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */
#define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */
#define MIPS_HFLAG_M16_SHIFT 10 #define MIPS_HFLAG_M16_SHIFT 10
/* If translation is interrupted between the branch instruction and /*
* If translation is interrupted between the branch instruction and
* the delay slot, record what type of branch it is so that we can * the delay slot, record what type of branch it is so that we can
* resume translation properly. It might be possible to reduce * resume translation properly. It might be possible to reduce
* this from three bits to two. */ * this from three bits to two.
*/
#define MIPS_HFLAG_BMASK_BASE 0x803800 #define MIPS_HFLAG_BMASK_BASE 0x803800
#define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */
#define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */
@ -1086,8 +1093,10 @@ extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
#define CPU_SAVE_VERSION 5 #define CPU_SAVE_VERSION 5
/* MMU modes definitions. We carefully match the indices with our /*
hflags layout. */ * MMU modes definitions. We carefully match the indices with our
* hflags layout.
*/
#define MMU_MODE0_SUFFIX _kernel #define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _super #define MMU_MODE1_SUFFIX _super
#define MMU_MODE2_SUFFIX _user #define MMU_MODE2_SUFFIX _user
@ -1110,7 +1119,8 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
#include "exec/cpu-all.h" #include "exec/cpu-all.h"
/* Memory access type : /*
* Memory access type :
* may be needed for precise access rights control and precise exceptions. * may be needed for precise access rights control and precise exceptions.
*/ */
enum { enum {