mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-07-07 17:00:35 +00:00
Merge branch 'master' of https://github.com/unicorn-engine/unicorn
This commit is contained in:
Nguyen Anh Quynh
commit
9cd7e2fbf6
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@ -260,22 +260,22 @@ int x86_reg_read(struct uc_struct *uc, unsigned int regid, void *value)
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.eip);
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.eip);
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break;
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break;
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case UC_X86_REG_CS:
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case UC_X86_REG_CS:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_CS].base;
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.segs[R_CS].base;
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break;
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break;
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case UC_X86_REG_DS:
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case UC_X86_REG_DS:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_DS].base;
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.segs[R_DS].base;
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break;
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break;
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case UC_X86_REG_SS:
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case UC_X86_REG_SS:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_SS].base;
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.segs[R_SS].base;
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break;
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break;
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case UC_X86_REG_ES:
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case UC_X86_REG_ES:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_ES].base;
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.segs[R_ES].base;
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break;
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break;
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case UC_X86_REG_FS:
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case UC_X86_REG_FS:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_FS].base;
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.segs[R_FS].base;
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break;
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break;
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case UC_X86_REG_GS:
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case UC_X86_REG_GS:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_GS].base;
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.segs[R_GS].base;
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break;
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break;
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}
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}
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break;
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break;
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@ -412,22 +412,22 @@ int x86_reg_read(struct uc_struct *uc, unsigned int regid, void *value)
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.eip);
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.eip);
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break;
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break;
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case UC_X86_REG_CS:
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case UC_X86_REG_CS:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_CS].base;
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*(int64_t *)value = X86_CPU(uc, mycpu)->env.segs[R_CS].base;
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break;
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break;
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case UC_X86_REG_DS:
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case UC_X86_REG_DS:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_DS].base;
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*(int64_t *)value = X86_CPU(uc, mycpu)->env.segs[R_DS].base;
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break;
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break;
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case UC_X86_REG_SS:
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case UC_X86_REG_SS:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_SS].base;
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*(int64_t *)value = X86_CPU(uc, mycpu)->env.segs[R_SS].base;
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break;
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break;
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case UC_X86_REG_ES:
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case UC_X86_REG_ES:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_ES].base;
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*(int64_t *)value = X86_CPU(uc, mycpu)->env.segs[R_ES].base;
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break;
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break;
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case UC_X86_REG_FS:
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case UC_X86_REG_FS:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_FS].base;
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*(int64_t *)value = X86_CPU(uc, mycpu)->env.segs[R_FS].base;
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break;
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break;
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case UC_X86_REG_GS:
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case UC_X86_REG_GS:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_GS].base;
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*(int64_t *)value = X86_CPU(uc, mycpu)->env.segs[R_GS].base;
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break;
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break;
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case UC_X86_REG_R8:
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case UC_X86_REG_R8:
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*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[8]);
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*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[8]);
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@ -660,22 +660,22 @@ int x86_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
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WRITE_WORD(X86_CPU(uc, mycpu)->env.eip, *(uint16_t *)value);
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WRITE_WORD(X86_CPU(uc, mycpu)->env.eip, *(uint16_t *)value);
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break;
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break;
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case UC_X86_REG_CS:
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case UC_X86_REG_CS:
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X86_CPU(uc, mycpu)->env.segs[R_CS].base = *(uint16_t *)value;
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X86_CPU(uc, mycpu)->env.segs[R_CS].base = *(uint32_t *)value;
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break;
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break;
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case UC_X86_REG_DS:
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case UC_X86_REG_DS:
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X86_CPU(uc, mycpu)->env.segs[R_DS].base = *(uint16_t *)value;
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X86_CPU(uc, mycpu)->env.segs[R_DS].base = *(uint32_t *)value;
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break;
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break;
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case UC_X86_REG_SS:
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case UC_X86_REG_SS:
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X86_CPU(uc, mycpu)->env.segs[R_SS].base = *(uint16_t *)value;
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X86_CPU(uc, mycpu)->env.segs[R_SS].base = *(uint32_t *)value;
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break;
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break;
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case UC_X86_REG_ES:
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case UC_X86_REG_ES:
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X86_CPU(uc, mycpu)->env.segs[R_ES].base = *(uint16_t *)value;
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X86_CPU(uc, mycpu)->env.segs[R_ES].base = *(uint32_t *)value;
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break;
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break;
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case UC_X86_REG_FS:
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case UC_X86_REG_FS:
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X86_CPU(uc, mycpu)->env.segs[R_FS].base = *(uint16_t *)value;
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X86_CPU(uc, mycpu)->env.segs[R_FS].base = *(uint32_t *)value;
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break;
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break;
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case UC_X86_REG_GS:
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case UC_X86_REG_GS:
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X86_CPU(uc, mycpu)->env.segs[R_GS].base = *(uint16_t *)value;
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X86_CPU(uc, mycpu)->env.segs[R_GS].base = *(uint32_t *)value;
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break;
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break;
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}
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}
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break;
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break;
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@ -812,22 +812,22 @@ int x86_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
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WRITE_WORD(X86_CPU(uc, mycpu)->env.eip, *(uint16_t *)value);
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WRITE_WORD(X86_CPU(uc, mycpu)->env.eip, *(uint16_t *)value);
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break;
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break;
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case UC_X86_REG_CS:
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case UC_X86_REG_CS:
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X86_CPU(uc, mycpu)->env.segs[R_CS].base = *(uint16_t *)value;
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X86_CPU(uc, mycpu)->env.segs[R_CS].base = *(uint64_t *)value;
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break;
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break;
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case UC_X86_REG_DS:
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case UC_X86_REG_DS:
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X86_CPU(uc, mycpu)->env.segs[R_DS].base = *(uint16_t *)value;
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X86_CPU(uc, mycpu)->env.segs[R_DS].base = *(uint64_t *)value;
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break;
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break;
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case UC_X86_REG_SS:
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case UC_X86_REG_SS:
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X86_CPU(uc, mycpu)->env.segs[R_SS].base = *(uint16_t *)value;
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X86_CPU(uc, mycpu)->env.segs[R_SS].base = *(uint64_t *)value;
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break;
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break;
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case UC_X86_REG_ES:
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case UC_X86_REG_ES:
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X86_CPU(uc, mycpu)->env.segs[R_ES].base = *(uint16_t *)value;
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X86_CPU(uc, mycpu)->env.segs[R_ES].base = *(uint64_t *)value;
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break;
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break;
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case UC_X86_REG_FS:
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case UC_X86_REG_FS:
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X86_CPU(uc, mycpu)->env.segs[R_FS].base = *(uint16_t *)value;
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X86_CPU(uc, mycpu)->env.segs[R_FS].base = *(uint64_t *)value;
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break;
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break;
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case UC_X86_REG_GS:
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case UC_X86_REG_GS:
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X86_CPU(uc, mycpu)->env.segs[R_GS].base = *(uint16_t *)value;
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X86_CPU(uc, mycpu)->env.segs[R_GS].base = *(uint64_t *)value;
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break;
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break;
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case UC_X86_REG_R8:
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case UC_X86_REG_R8:
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X86_CPU(uc, mycpu)->env.regs[8] = *(uint64_t *)value;
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X86_CPU(uc, mycpu)->env.regs[8] = *(uint64_t *)value;
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@ -1,7 +1,7 @@
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#!/usr/bin/env python
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#!/usr/bin/env python
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# reg_write() can't modify PC from within trace callbacks
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# reg_write() can't modify PC from within trace callbacks
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# Pull Request #4
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# issue #210
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from __future__ import print_function
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from __future__ import print_function
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from unicorn import *
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from unicorn import *
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@ -30,11 +30,7 @@ def hook_block(uc, address, size, user_data):
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class CallBackPCTest(regress.RegressTest):
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class CallBackPCTest(regress.RegressTest):
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def runTest(self):
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def test_instruction_trace(self):
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self.instruction_trace_test()
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# set up emulation
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def instruction_trace_test(self):
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try:
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try:
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# initialize emulator in ARM's Thumb mode
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# initialize emulator in ARM's Thumb mode
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mu = Uc(UC_ARCH_ARM, UC_MODE_THUMB)
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mu = Uc(UC_ARCH_ARM, UC_MODE_THUMB)
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@ -51,14 +47,44 @@ class CallBackPCTest(regress.RegressTest):
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# tracing all instructions with customized callback
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# tracing all instructions with customized callback
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mu.hook_add(UC_HOOK_CODE, hook_code, user_data=mu)
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mu.hook_add(UC_HOOK_CODE, hook_code, user_data=mu)
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# tracing all basic blocks with customized callback
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# emulate one instruction
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mu.hook_add(UC_HOOK_BLOCK, hook_block, user_data=mu)
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mu.emu_start(BASE_ADDRESS, BASE_ADDRESS + len(THUMB_CODE), count=1)
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# emulate machine code in infinite time
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# the instruction trace callback set PC to 0xffffffff, so at this
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mu.emu_start(BASE_ADDRESS, BASE_ADDRESS + len(THUMB_CODE))
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# point, the PC value should be 0xffffffff.
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pc = mu.reg_read(UC_ARM_REG_PC)
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self.assertEqual(pc, 0xffffffff, "PC not set to 0xffffffff by instruction trace callback")
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except UcError as e:
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except UcError as e:
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assertFalse(0, "ERROR: %s" % e)
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self.assertFalse(0, "ERROR: %s" % e)
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def test_block_trace(self):
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try:
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# initialize emulator in ARM's Thumb mode
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mu = Uc(UC_ARCH_ARM, UC_MODE_THUMB)
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# map some memory
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mu.mem_map(BASE_ADDRESS, 2 * 1024 * 1024)
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# write machine code to be emulated to memory
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mu.mem_write(BASE_ADDRESS, THUMB_CODE)
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# setup stack
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mu.reg_write(UC_ARM_REG_SP, BASE_ADDRESS + 2 * 1024 * 1024)
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# trace blocks with customized callback
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mu.hook_add(UC_HOOK_BLOCK, hook_block, user_data=mu)
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# emulate one instruction
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mu.emu_start(BASE_ADDRESS, BASE_ADDRESS + len(THUMB_CODE), count=1)
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# the block callback set PC to 0xffffffff, so at this point, the PC
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# value should be 0xffffffff.
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pc = mu.reg_read(UC_ARM_REG_PC)
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self.assertEqual(pc, 0xffffffff, "PC not set to 0xffffffff by block callback")
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except UcError as e:
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self.assertFalse(0, "ERROR: %s" % e)
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if __name__ == '__main__':
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if __name__ == '__main__':
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regress.main()
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regress.main()
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