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target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word

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Separate shift + extract low will result in one extra insn
for hosts like RISC-V, MIPS, and Sparc.

Backports commit 664b7e3b97d6376f3329986c465b3782458b0f8b from qemu
This commit is contained in:
Richard Henderson 2019-11-18 20:36:15 -05:00 committed by Lioncash
parent 93c016a3e7
commit 9d2a3064af
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 6 additions and 12 deletions
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18
qemu/target/arm/translate.c
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@ -1851,8 +1851,7 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
if (insn & ARM_CP_RW_BIT) { /* TMRRC */
iwmmxt_load_reg(s, s->V0, wrd);
tcg_gen_extrl_i64_i32(tcg_ctx, tcg_ctx->cpu_R[rdlo], s->V0);
tcg_gen_shri_i64(tcg_ctx, s->V0, s->V0, 32);
tcg_gen_extrl_i64_i32(tcg_ctx, tcg_ctx->cpu_R[rdhi], s->V0);
tcg_gen_extrh_i64_i32(tcg_ctx, tcg_ctx->cpu_R[rdhi], s->V0);
} else { /* TMCRR */
tcg_gen_concat_i32_i64(tcg_ctx, s->V0, tcg_ctx->cpu_R[rdlo], tcg_ctx->cpu_R[rdhi]);
iwmmxt_store_reg(s, s->V0, wrd);
@ -2898,8 +2897,7 @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
if (insn & ARM_CP_RW_BIT) { /* MRA */
iwmmxt_load_reg(s, s->V0, acc);
tcg_gen_extrl_i64_i32(tcg_ctx, tcg_ctx->cpu_R[rdlo], s->V0);
tcg_gen_shri_i64(tcg_ctx, s->V0, s->V0, 32);
tcg_gen_extrl_i64_i32(tcg_ctx, tcg_ctx->cpu_R[rdhi], s->V0);
tcg_gen_extrh_i64_i32(tcg_ctx, tcg_ctx->cpu_R[rdhi], s->V0);
tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_R[rdhi], tcg_ctx->cpu_R[rdhi], (1 << (40 - 32)) - 1);
} else { /* MAR */
tcg_gen_concat_i32_i64(tcg_ctx, s->V0, tcg_ctx->cpu_R[rdlo], tcg_ctx->cpu_R[rdhi]);
@ -6145,8 +6143,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
gen_helper_neon_narrow_high_u16(tcg_ctx, tmp, s->V0);
break;
case 2:
tcg_gen_shri_i64(tcg_ctx, s->V0, s->V0, 32);
tcg_gen_extrl_i64_i32(tcg_ctx, tmp, s->V0);
tcg_gen_extrh_i64_i32(tcg_ctx, tmp, s->V0);
break;
default: abort();
}
@ -6160,8 +6157,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
break;
case 2:
tcg_gen_addi_i64(tcg_ctx, s->V0, s->V0, 1u << 31);
tcg_gen_shri_i64(tcg_ctx, s->V0, s->V0, 32);
tcg_gen_extrl_i64_i32(tcg_ctx, tmp, s->V0);
tcg_gen_extrh_i64_i32(tcg_ctx, tmp, s->V0);
break;
default: abort();
}
@ -7400,9 +7396,8 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
tmp = tcg_temp_new_i32(tcg_ctx);
tcg_gen_extrl_i64_i32(tcg_ctx, tmp, tmp64);
store_reg(s, rt, tmp);
tcg_gen_shri_i64(tcg_ctx, tmp64, tmp64, 32);
tmp = tcg_temp_new_i32(tcg_ctx);
tcg_gen_extrl_i64_i32(tcg_ctx, tmp, tmp64);
tcg_gen_extrh_i64_i32(tcg_ctx, tmp, tmp64);
tcg_temp_free_i64(tcg_ctx, tmp64);
store_reg(s, rt2, tmp);
} else {
@ -7513,8 +7508,7 @@ static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
tcg_gen_extrl_i64_i32(tcg_ctx, tmp, val);
store_reg(s, rlow, tmp);
tmp = tcg_temp_new_i32(tcg_ctx);
tcg_gen_shri_i64(tcg_ctx, val, val, 32);
tcg_gen_extrl_i64_i32(tcg_ctx, tmp, val);
tcg_gen_extrh_i64_i32(tcg_ctx, tmp, val);
store_reg(s, rhigh, tmp);
}