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unicorn/mips: Lessen the amount of MIPS_CPU macro usage
Syntaxically reduces line noise
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parent
be260c43b6
commit
9e14a824ed
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@ -39,17 +39,19 @@ static uint64_t mips_mem_redirect(uint64_t address)
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static void mips_set_pc(struct uc_struct *uc, uint64_t address)
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static void mips_set_pc(struct uc_struct *uc, uint64_t address)
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{
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{
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((CPUMIPSState *)uc->current_cpu->env_ptr)->active_tc.PC = address;
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CPUMIPSState *state = uc->cpu->env_ptr;
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state->active_tc.PC = address;
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}
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}
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void mips_release(void *ctx);
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void mips_release(void *ctx);
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void mips_release(void *ctx)
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void mips_release(void *ctx)
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{
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{
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MIPSCPU* cpu;
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TCGContext *tcg_ctx = (TCGContext *) ctx;
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TCGContext *tcg_ctx = (TCGContext *) ctx;
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MIPSCPU *cpu = MIPS_CPU(tcg_ctx->uc, tcg_ctx->uc->cpu);
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release_common(ctx);
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release_common(ctx);
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cpu = MIPS_CPU(tcg_ctx->uc, tcg_ctx->uc->cpu);
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g_free(cpu->env.tlb);
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g_free(cpu->env.tlb);
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g_free(cpu->env.mvp);
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g_free(cpu->env.mvp);
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g_free(tcg_ctx->tb_ctx.tbs);
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g_free(tcg_ctx->tb_ctx.tbs);
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@ -57,9 +59,8 @@ void mips_release(void *ctx)
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void mips_reg_reset(struct uc_struct *uc)
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void mips_reg_reset(struct uc_struct *uc)
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{
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{
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CPUArchState *env;
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CPUArchState *env = uc->cpu->env_ptr;
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(void)uc;
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env = uc->cpu->env_ptr;
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memset(env->active_tc.gpr, 0, sizeof(env->active_tc.gpr));
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memset(env->active_tc.gpr, 0, sizeof(env->active_tc.gpr));
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env->active_tc.PC = 0;
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env->active_tc.PC = 0;
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@ -68,18 +69,19 @@ void mips_reg_reset(struct uc_struct *uc)
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int mips_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count)
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int mips_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count)
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{
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{
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CPUState *mycpu = uc->cpu;
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CPUState *mycpu = uc->cpu;
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CPUMIPSState *state = &MIPS_CPU(uc, mycpu)->env;
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int i;
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int i;
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for (i = 0; i < count; i++) {
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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unsigned int regid = regs[i];
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void *value = vals[i];
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void *value = vals[i];
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if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31)
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if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31) {
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*(mipsreg_t *)value = MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - UC_MIPS_REG_0];
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*(mipsreg_t *)value = state->active_tc.gpr[regid - UC_MIPS_REG_0];
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else {
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} else {
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switch(regid) {
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switch(regid) {
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default: break;
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default: break;
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case UC_MIPS_REG_PC:
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case UC_MIPS_REG_PC:
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*(mipsreg_t *)value = MIPS_CPU(uc, mycpu)->env.active_tc.PC;
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*(mipsreg_t *)value = state->active_tc.PC;
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break;
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break;
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}
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}
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}
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}
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@ -91,18 +93,19 @@ int mips_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int cou
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int mips_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, int count)
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int mips_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, int count)
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{
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{
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CPUState *mycpu = uc->cpu;
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CPUState *mycpu = uc->cpu;
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CPUMIPSState *state = &MIPS_CPU(uc, mycpu)->env;
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int i;
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int i;
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for (i = 0; i < count; i++) {
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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unsigned int regid = regs[i];
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const void *value = vals[i];
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const void *value = vals[i];
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if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31)
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if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31) {
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MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - UC_MIPS_REG_0] = *(mipsreg_t *)value;
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state->active_tc.gpr[regid - UC_MIPS_REG_0] = *(mipsreg_t *)value;
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else {
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} else {
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switch(regid) {
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switch(regid) {
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default: break;
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default: break;
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case UC_MIPS_REG_PC:
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case UC_MIPS_REG_PC:
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MIPS_CPU(uc, mycpu)->env.active_tc.PC = *(mipsreg_t *)value;
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state->active_tc.PC = *(mipsreg_t *)value;
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// force to quit execution and flush TB
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// force to quit execution and flush TB
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uc->quit_request = true;
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uc->quit_request = true;
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uc_emu_stop(uc);
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uc_emu_stop(uc);
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