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target/mips: Add emulation of nanoMIPS 16-bit misc instructions

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Add emulation of misc nanoMIPS 16-bit instructions.

Backports commit 8869ad02bfd9737f6a8fceab5ca286eaa899b790 from qemu
This commit is contained in:
Yongbok Kim 2018-08-27 04:31:33 -04:00 committed by Lioncash
parent 25d95b6971
commit 9e82494344
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 35 additions and 0 deletions
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35
qemu/target/mips/translate.c
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@ -16875,6 +16875,41 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
op = extract32(ctx->opcode, 10, 6); op = extract32(ctx->opcode, 10, 6);
switch (op) { switch (op) {
case NM_P16_MV: case NM_P16_MV:
rt = NANOMIPS_EXTRACT_RD5(ctx->opcode);
if (rt != 0) {
/* MOVE */
rs = NANOMIPS_EXTRACT_RS5(ctx->opcode);
gen_arith(ctx, OPC_ADDU, rt, rs, 0);
} else {
/* P16.RI */
switch (extract32(ctx->opcode, 3, 2)) {
case NM_P16_SYSCALL:
if (extract32(ctx->opcode, 2, 1) == 0) {
generate_exception_end(ctx, EXCP_SYSCALL);
} else {
generate_exception_end(ctx, EXCP_RI);
}
break;
case NM_BREAK16:
generate_exception_end(ctx, EXCP_BREAK);
break;
case NM_SDBBP16:
// Unicorn: commented out
/* if (is_uhi(extract32(ctx->opcode, 0, 3))) {
gen_helper_do_semihosting(cpu_env);
} else */ {
if (ctx->hflags & MIPS_HFLAG_SBRI) {
generate_exception_end(ctx, EXCP_RI);
} else {
generate_exception_end(ctx, EXCP_DBp);
}
}
break;
default:
generate_exception_end(ctx, EXCP_RI);
break;
}
}
break; break;
case NM_P16_SHIFT: case NM_P16_SHIFT:
{ {