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target/riscv: Convert RV32F insns to decodetree

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Backports commit 6f0e74ff4b7f83901e99e59108eaa43513a0ce36 from qemu
This commit is contained in:
Bastian Koppelmann 2019-03-18 16:33:32 -04:00 committed by Lioncash
parent 3f9177f6e7
commit 9edaf2069e
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GPG key ID: 4E3C3CC1031BA9C7
4 changed files with 523 additions and 0 deletions
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58
qemu/target/riscv/insn32-64.decode Normal file
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@ -0,0 +1,58 @@
#
# RISC-V translation routines for the RV Instruction Set.
#
# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
#
# This program is free software; you can redistribute it and/or modify it
# under the terms and conditions of the GNU General Public License,
# version 2 or later, as published by the Free Software Foundation.
#
# This program is distributed in the hope it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details.
#
# You should have received a copy of the GNU General Public License along with
# this program. If not, see <http://www.gnu.org/licenses/>.
# This is concatenated with insn32.decode for risc64 targets.
# Most of the fields and formats are there.
%sh5 20:5
@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
# *** RV64I Base Instruction Set (in addition to RV32I) ***
lwu ............ ..... 110 ..... 0000011 @i
ld ............ ..... 011 ..... 0000011 @i
sd ....... ..... ..... 011 ..... 0100011 @s
addiw ............ ..... 000 ..... 0011011 @i
slliw 0000000 ..... ..... 001 ..... 0011011 @sh5
srliw 0000000 ..... ..... 101 ..... 0011011 @sh5
sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5
addw 0000000 ..... ..... 000 ..... 0111011 @r
subw 0100000 ..... ..... 000 ..... 0111011 @r
sllw 0000000 ..... ..... 001 ..... 0111011 @r
srlw 0000000 ..... ..... 101 ..... 0111011 @r
sraw 0100000 ..... ..... 101 ..... 0111011 @r
# *** RV64M Standard Extension (in addition to RV32M) ***
mulw 0000001 ..... ..... 000 ..... 0111011 @r
divw 0000001 ..... ..... 100 ..... 0111011 @r
divuw 0000001 ..... ..... 101 ..... 0111011 @r
remw 0000001 ..... ..... 110 ..... 0111011 @r
remuw 0000001 ..... ..... 111 ..... 0111011 @r
# *** RV64A Standard Extension (in addition to RV32A) ***
lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st
amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st
amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st
amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st
amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st
amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st
amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st

35
qemu/target/riscv/insn32.decode
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@ -17,12 +17,14 @@
# this program. If not, see <http://www.gnu.org/licenses/>.
# Fields:
%rs3 27:5
%rs2 20:5
%rs1 15:5
%rd 7:5
%sh10 20:10
%csr 20:12
%rm 12:3
# immediates:
%imm_i 20:s12
@ -50,6 +52,11 @@
@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
auipc .................... ..... 0010111 @u
@ -119,3 +126,31 @@ amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
# *** RV32F Standard Extension ***
flw ............ ..... 010 ..... 0000111 @i
fsw ....... ..... ..... 010 ..... 0100111 @s
fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm
fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm
fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm
fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm
fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm
fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm
fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm
fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm
fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm
fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r
fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r
fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r
fmin_s 0010100 ..... ..... 000 ..... 1010011 @r
fmax_s 0010100 ..... ..... 001 ..... 1010011 @r
fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm
fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm
fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2
feq_s 1010000 ..... ..... 010 ..... 1010011 @r
flt_s 1010000 ..... ..... 001 ..... 1010011 @r
fle_s 1010000 ..... ..... 000 ..... 1010011 @r
fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2

429
qemu/target/riscv/insn_trans/trans_rvf.inc.c Normal file
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@ -0,0 +1,429 @@
/*
* RISC-V translation routines for the RV64F Standard Extension.
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
* Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
* Bastian Koppelmann, kbastian@mail.uni-paderborn.de
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#define REQUIRE_FPU do {\
if (ctx->mstatus_fs == 0) \
return false; \
} while (0)
static bool trans_flw(DisasContext *ctx, arg_flw *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(ctx, t0, a->rs1);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm);
tcg_gen_qemu_ld_i64(ctx->uc, tcg_ctx->cpu_fpr_risc[a->rd], t0, ctx->mem_idx, MO_TEUL);
/* RISC-V requires NaN-boxing of narrower width floating point values */
tcg_gen_ori_i64(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_fpr_risc[a->rd], 0xffffffff00000000ULL);
tcg_temp_free(tcg_ctx, t0);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(ctx, t0, a->rs1);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm);
tcg_gen_qemu_st_i64(ctx->uc, tcg_ctx->cpu_fpr_risc[a->rs2], t0, ctx->mem_idx, MO_TEUL);
tcg_temp_free(tcg_ctx, t0);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
gen_set_rm(ctx, a->rm);
gen_helper_fmadd_s(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr_risc[a->rs1],
tcg_ctx->cpu_fpr_risc[a->rs2], tcg_ctx->cpu_fpr_risc[a->rs3]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
gen_set_rm(ctx, a->rm);
gen_helper_fmsub_s(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr_risc[a->rs1],
tcg_ctx->cpu_fpr_risc[a->rs2], tcg_ctx->cpu_fpr_risc[a->rs3]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
gen_set_rm(ctx, a->rm);
gen_helper_fnmsub_s(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr_risc[a->rs1],
tcg_ctx->cpu_fpr_risc[a->rs2], tcg_ctx->cpu_fpr_risc[a->rs3]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
gen_set_rm(ctx, a->rm);
gen_helper_fnmadd_s(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr_risc[a->rs1],
tcg_ctx->cpu_fpr_risc[a->rs2], tcg_ctx->cpu_fpr_risc[a->rs3]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
gen_set_rm(ctx, a->rm);
gen_helper_fadd_s(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_env,
tcg_ctx->cpu_fpr_risc[a->rs1], tcg_ctx->cpu_fpr_risc[a->rs2]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
gen_set_rm(ctx, a->rm);
gen_helper_fsub_s(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_env,
tcg_ctx->cpu_fpr_risc[a->rs1], tcg_ctx->cpu_fpr_risc[a->rs2]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
gen_set_rm(ctx, a->rm);
gen_helper_fmul_s(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_env,
tcg_ctx->cpu_fpr_risc[a->rs1], tcg_ctx->cpu_fpr_risc[a->rs2]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
gen_set_rm(ctx, a->rm);
gen_helper_fdiv_s(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_env,
tcg_ctx->cpu_fpr_risc[a->rs1], tcg_ctx->cpu_fpr_risc[a->rs2]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
gen_set_rm(ctx, a->rm);
gen_helper_fsqrt_s(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr_risc[a->rs1]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
if (a->rs1 == a->rs2) { /* FMOV */
tcg_gen_mov_i64(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_fpr_risc[a->rs1]);
} else { /* FSGNJ */
tcg_gen_deposit_i64(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_fpr_risc[a->rs2], tcg_ctx->cpu_fpr_risc[a->rs1],
0, 31);
}
mark_fs_dirty(ctx);
return true;
}
static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
if (a->rs1 == a->rs2) { /* FNEG */
tcg_gen_xori_i64(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_fpr_risc[a->rs1], INT32_MIN);
} else {
TCGv_i64 t0 = tcg_temp_new_i64(tcg_ctx);
tcg_gen_not_i64(tcg_ctx, t0, tcg_ctx->cpu_fpr_risc[a->rs2]);
tcg_gen_deposit_i64(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], t0, tcg_ctx->cpu_fpr_risc[a->rs1], 0, 31);
tcg_temp_free_i64(tcg_ctx, t0);
}
mark_fs_dirty(ctx);
return true;
}
static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
if (a->rs1 == a->rs2) { /* FABS */
tcg_gen_andi_i64(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_fpr_risc[a->rs1], ~INT32_MIN);
} else {
TCGv_i64 t0 = tcg_temp_new_i64(tcg_ctx);
tcg_gen_andi_i64(tcg_ctx, t0, tcg_ctx->cpu_fpr_risc[a->rs2], INT32_MIN);
tcg_gen_xor_i64(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_fpr_risc[a->rs1], t0);
tcg_temp_free_i64(tcg_ctx, t0);
}
mark_fs_dirty(ctx);
return true;
}
static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
gen_helper_fmin_s(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr_risc[a->rs1],
tcg_ctx->cpu_fpr_risc[a->rs2]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
gen_helper_fmax_s(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_env, tcg_ctx->cpu_fpr_risc[a->rs1],
tcg_ctx->cpu_fpr_risc[a->rs2]);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_w_s(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->cpu_fpr_risc[a->rs1]);
gen_set_gpr(ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_wu_s(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->cpu_fpr_risc[a->rs1]);
gen_set_gpr(ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
/* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGv t0 = tcg_temp_new(tcg_ctx);
#if defined(TARGET_RISCV64)
tcg_gen_ext32s_tl(tcg_ctx, t0, tcg_ctx->cpu_fpr_risc[a->rs1]);
#else
tcg_gen_extrl_i64_i32(tcg_ctx, t0, tcg_ctx->cpu_fpr_risc[a->rs1]);
#endif
gen_set_gpr(ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_helper_feq_s(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->cpu_fpr_risc[a->rs1], tcg_ctx->cpu_fpr_risc[a->rs2]);
gen_set_gpr(ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_helper_flt_s(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->cpu_fpr_risc[a->rs1], tcg_ctx->cpu_fpr_risc[a->rs2]);
gen_set_gpr(ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_helper_fle_s(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->cpu_fpr_risc[a->rs1], tcg_ctx->cpu_fpr_risc[a->rs2]);
gen_set_gpr(ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_helper_fclass_s(tcg_ctx, t0, tcg_ctx->cpu_fpr_risc[a->rs1]);
gen_set_gpr(ctx, a->rd, t0);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(ctx, t0, a->rs1);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_s_w(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_env, t0);
mark_fs_dirty(ctx);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(ctx, t0, a->rs1);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_s_wu(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_env, t0);
mark_fs_dirty(ctx);
tcg_temp_free(tcg_ctx, t0);
return true;
}
static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
/* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(ctx, t0, a->rs1);
#if defined(TARGET_RISCV64)
tcg_gen_mov_i64(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], t0);
#else
tcg_gen_extu_i32_i64(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], t0);
#endif
mark_fs_dirty(ctx);
tcg_temp_free(tcg_ctx, t0);
return true;
}

1
qemu/target/riscv/translate.c
View file

@ -1786,6 +1786,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
#include "insn_trans/trans_rva.inc.c"
#include "insn_trans/trans_rvf.inc.c"
static void decode_RV32_64G(DisasContext *ctx)
{