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target/mips: Clean up handling of CP0 register 26
Clean up handling of CP0 register 26. Backports commit dbbf08b2892a7cf93e47f84c512953234a452cec from qemu
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7f23faefa3
commit
9fe6520144
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@ -422,7 +422,7 @@ typedef struct mips_def_t mips_def_t;
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#define CP0_REG25__PERFCTL3 6
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#define CP0_REG25__PERFCNT3 7
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/* CP0 Register 26 */
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#define CP0_REG00__ERRCTL 0
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#define CP0_REG26__ERRCTL 0
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/* CP0 Register 27 */
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#define CP0_REG27__CACHERR 0
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/* CP0 Register 28 */
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@ -7535,7 +7535,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_26:
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switch (sel) {
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case 0:
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case CP0_REG26__ERRCTL:
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gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_ErrCtl));
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register_name = "ErrCtl";
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break;
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@ -8293,7 +8293,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_26:
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switch (sel) {
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case 0:
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case CP0_REG26__ERRCTL:
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gen_helper_mtc0_errctl(tcg_ctx, tcg_ctx->cpu_env, arg);
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ctx->base.is_jmp = DISAS_STOP;
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register_name = "ErrCtl";
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@ -9020,7 +9020,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_26:
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switch (sel) {
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case 0:
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case CP0_REG26__ERRCTL:
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gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_ErrCtl));
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register_name = "ErrCtl";
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break;
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@ -9756,7 +9756,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_26:
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switch (sel) {
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case 0:
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case CP0_REG26__ERRCTL:
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gen_helper_mtc0_errctl(tcg_ctx, tcg_ctx->cpu_env, arg);
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ctx->base.is_jmp = DISAS_STOP;
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register_name = "ErrCtl";
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