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target/arm: Improve debug logging of AArch32 exception return

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For AArch32, exception return happens through certain kinds
of CPSR write. We don't currently have any CPU_LOG_INT logging
of these events (unlike AArch64, where we log in the ERET
instruction). Add some suitable logging.

This will log exception returns like this:
Exception return from AArch32 hyp to usr PC 0x80100374

paralleling the existing logging in the exception_return
helper for AArch64 exception returns:
Exception return from AArch64 EL2 to AArch64 EL0 PC 0x8003045c
Exception return from AArch64 EL2 to AArch32 EL0 PC 0x8003045c

(Note that an AArch32 exception return can only be
AArch32->AArch32, never to AArch64.)

Backports commit 81e3728407bf4a12f83e14fd410d5f0a7d29b5b4 from qemu
This commit is contained in:
Lioncash 2018-11-10 09:09:47 -05:00
parent 03ec90f39b
commit a0358202a7
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 33 additions and 8 deletions
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16
qemu/target/arm/helper.c
View file

@ -47,6 +47,8 @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address,
V8M_SAttributes *sattrs); V8M_SAttributes *sattrs);
#endif #endif
static void switch_mode(CPUARMState *env, int mode);
static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
{ {
assert(ri->fieldoffset); assert(ri->fieldoffset);
@ -5390,8 +5392,18 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
arm_feature(env, ARM_FEATURE_V8)) { arm_feature(env, ARM_FEATURE_V8)) {
mask |= CPSR_IL; mask |= CPSR_IL;
val |= CPSR_IL; val |= CPSR_IL;
qemu_log_mask(LOG_GUEST_ERROR,
"Illegal AArch32 mode switch attempt from %s to %s\n",
aarch32_mode_name(env->uncached_cpsr),
aarch32_mode_name(val));
} }
} else { } else {
qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n",
write_type == CPSRWriteExceptionReturn ?
"Exception return from AArch32" :
"AArch32 mode switch from",
aarch32_mode_name(env->uncached_cpsr),
aarch32_mode_name(val), env->regs[15]);
switch_mode(env, val & CPSR_M); switch_mode(env, val & CPSR_M);
} }
} }
@ -5489,7 +5501,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
return 0; return 0;
} }
void switch_mode(CPUARMState *env, int mode) static void switch_mode(CPUARMState *env, int mode)
{ {
ARMCPU *cpu = arm_env_get_cpu(env); ARMCPU *cpu = arm_env_get_cpu(env);
@ -5511,7 +5523,7 @@ void aarch64_sync_64_to_32(CPUARMState *env)
#else #else
void switch_mode(CPUARMState *env, int mode) static void switch_mode(CPUARMState *env, int mode)
{ {
int old_mode; int old_mode;
int i; int i;

19
qemu/target/arm/internals.h
View file

@ -147,7 +147,6 @@ static inline int bank_number(int mode)
g_assert_not_reached(); g_assert_not_reached();
} }
void switch_mode(CPUARMState *, int);
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
void arm_translate_init(struct uc_struct *uc); void arm_translate_init(struct uc_struct *uc);
@ -842,4 +841,22 @@ static inline uint32_t v7m_sp_limit(CPUARMState *env)
} }
} }
/**
* aarch32_mode_name(): Return name of the AArch32 CPU mode
* @psr: Program Status Register indicating CPU mode
*
* Returns, for debug logging purposes, a printable representation
* of the AArch32 CPU mode ("svc", "usr", etc) as indicated by
* the low bits of the specified PSR.
*/
static inline const char *aarch32_mode_name(uint32_t psr)
{
static const char cpu_mode_names[16][4] = {
"usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
"???", "???", "hyp", "und", "???", "???", "???", "sys"
};
return cpu_mode_names[psr & 0xf];
}
#endif #endif

6
qemu/target/arm/translate.c
View file

@ -13319,10 +13319,6 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
} }
#if 0 #if 0
static const char *cpu_mode_names[16] = {
"usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
"???", "???", "hyp", "und", "???", "???", "???", "sys"
};
void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
int flags) int flags)
@ -13389,7 +13385,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
psr & CPSR_V ? 'V' : '-', psr & CPSR_V ? 'V' : '-',
psr & CPSR_T ? 'T' : 'A', psr & CPSR_T ? 'T' : 'A',
ns_status, ns_status,
cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
} }
if (flags & CPU_DUMP_FPU) { if (flags & CPU_DUMP_FPU) {