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tcg/aarch64: Fix addsub2 for 0+C

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When al == xzr, we cannot use addi/subi because that encodes xsp.
Force a zero into the temp register for that (rare) case.

Backports commit 028fbea47713f909d6ea761a457779a82b276247 from qemu
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Richard Henderson 2018-03-01 09:13:48 -05:00 committed by Lioncash
parent 337f57dd2c
commit a03666f2f2
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1 changed files with 9 additions and 0 deletions
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9
qemu/tcg/aarch64/tcg-target.inc.c
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@ -969,6 +969,15 @@ static inline void tcg_out_addsub2(TCGContext *s, int ext, TCGReg rl,
insn = I3401_SUBSI; insn = I3401_SUBSI;
bl = -bl; bl = -bl;
} }
if (unlikely(al == TCG_REG_XZR)) {
/* ??? We want to allow al to be zero for the benefit of
negation via subtraction. However, that leaves open the
possibility of adding 0+const in the low part, and the
immediate add instructions encode XSP not XZR. Don't try
anything more elaborate here than loading another zero. */
al = TCG_REG_TMP;
tcg_out_movi(s, ext, al, 0);
}
tcg_out_insn_3401(s, insn, ext, rl, al, bl); tcg_out_insn_3401(s, insn, ext, rl, al, bl);
} else { } else {
tcg_out_insn_3502(s, sub ? I3502_SUBS : I3502_ADDS, ext, rl, al, bl); tcg_out_insn_3502(s, sub ? I3502_SUBS : I3502_ADDS, ext, rl, al, bl);