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target/arm: Convert B, BL, BLX (immediate)
Backports commit 360144f3b99f9a626ffcc6b9d76537e3a3e0e708 from qemu
This commit is contained in:
Richard Henderson
Lioncash
parent
ed9b8ad2ea
commit
a119870e57
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@ -21,3 +21,11 @@
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# All insns that have 0xf in insn[31:28] are decoded here.
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# All of those that have a COND field in insn[31:28] are in a32.decode
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#
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&i !extern imm
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# Branch with Link and Exchange
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%imm24h 0:s24 24:1 !function=times_2
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BLX_i 1111 101 . ........................ &i imm=%imm24h
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@ -520,3 +520,11 @@ SMMLSR .... 0111 0101 .... .... .... 1111 .... @rdamn
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STM ---- 100 b:1 i:1 u:1 w:1 0 rn:4 list:16 &ldst_block
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LDM_a32 ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16 &ldst_block
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# Branch, branch with link
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%imm26 0:s24 !function=times_4
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@branch ---- .... ........................ &i imm=%imm26
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B .... 1010 ........................ @branch
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BL .... 1011 ........................ @branch
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@ -284,47 +284,55 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
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%msr_sysm 4:1 8:4
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%mrs_sysm 4:1 16:4
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%imm16_16_0 16:4 0:12
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%imm21 26:s1 11:1 13:1 16:6 0:11 !function=times_2
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&ci cond imm
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{
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# Group insn[25:23] = 111, which is cond=111x for the branch below,
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# or unconditional, which would be illegal for the branch.
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{
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YIELD 1111 0011 1010 1111 1000 0000 0000 0001
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WFE 1111 0011 1010 1111 1000 0000 0000 0010
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WFI 1111 0011 1010 1111 1000 0000 0000 0011
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# Hints
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{
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YIELD 1111 0011 1010 1111 1000 0000 0000 0001
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WFE 1111 0011 1010 1111 1000 0000 0000 0010
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WFI 1111 0011 1010 1111 1000 0000 0000 0011
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# TODO: Implement SEV, SEVL; may help SMP performance.
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# SEV 1111 0011 1010 1111 1000 0000 0000 0100
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# SEVL 1111 0011 1010 1111 1000 0000 0000 0101
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# TODO: Implement SEV, SEVL; may help SMP performance.
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# SEV 1111 0011 1010 1111 1000 0000 0000 0100
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# SEVL 1111 0011 1010 1111 1000 0000 0000 0101
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# The canonical nop ends in 0000 0000, but the whole rest
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# of the space is "reserved hint, behaves as nop".
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NOP 1111 0011 1010 1111 1000 0000 ---- ----
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}
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# Note that the v7m insn overlaps both the normal and banked insn.
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{
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MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \
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# The canonical nop ends in 0000 0000, but the whole rest
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# of the space is "reserved hint, behaves as nop".
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NOP 1111 0011 1010 1111 1000 0000 ---- ----
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}
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# Note that the v7m insn overlaps both the normal and banked insn.
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{
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MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \
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&mrs_bank sysm=%mrs_sysm
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MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg
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MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8
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}
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{
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MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \
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MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg
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MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8
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}
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{
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MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \
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&msr_bank sysm=%msr_sysm
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MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg
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MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8
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}
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BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r
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{
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# At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as for
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# every other encoding of SUBS. With v7VE, IMM=0 is redefined as ERET.
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# The distinction between the two only matters for Hyp mode.
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ERET 1111 0011 1101 1110 1000 1111 0000 0000
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SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \
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MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg
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MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8
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}
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BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r
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{
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# At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as for
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# every other encoding of SUBS. With v7VE, IMM=0 is redefined as ERET.
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# The distinction between the two only matters for Hyp mode.
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ERET 1111 0011 1101 1110 1000 1111 0000 0000
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SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \
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&s_rri_rot rot=0 s=1 rd=15 rn=14
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}
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SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i
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HVC 1111 0111 1110 .... 1000 .... .... .... \
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}
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SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i
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HVC 1111 0111 1110 .... 1000 .... .... .... \
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&i imm=%imm16_16_0
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UDF 1111 0111 1111 ---- 1010 ---- ---- ----
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UDF 1111 0111 1111 ---- 1010 ---- ---- ----
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}
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B_cond_thumb 1111 0. cond:4 ...... 10.0 ............ &ci imm=%imm21
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}
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# Load/store (register, immediate, literal)
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@ -573,3 +581,12 @@ STM_t32 1110 1000 10.0 .... ................ @ldstm i=1 b=0
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STM_t32 1110 1001 00.0 .... ................ @ldstm i=0 b=1
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LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0
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LDM_t32 1110 1001 00.1 .... ................ @ldstm i=0 b=1
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# Branches
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%imm24 26:s1 13:1 11:1 16:10 0:11 !function=t32_branch24
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@branch24 ................................ &i imm=%imm24
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B 1111 0. .......... 10.1 ............ @branch24
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BL 1111 0. .......... 11.1 ............ @branch24
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BLX_i 1111 0. .......... 11.0 ............ @branch24
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@ -7695,6 +7695,14 @@ static int t32_expandimm_imm(DisasContext *s, int x)
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return imm;
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}
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static int t32_branch24(DisasContext *s, int x)
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{
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/* Convert J1:J2 at x[22:21] to I2:I1, which involves I=J^~S. */
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x ^= !(x < 0) * (3 << 21);
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/* Append the final zero. */
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return x << 1;
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}
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/*
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* Include the generated decoders.
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*/
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@ -10364,6 +10372,51 @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a)
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return do_ldm(s, a, 2);
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}
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/*
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* Branch, branch with link
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*/
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static bool trans_B(DisasContext *s, arg_i *a)
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{
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gen_jmp(s, read_pc(s) + a->imm);
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return true;
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}
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static bool trans_B_cond_thumb(DisasContext *s, arg_ci *a)
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{
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/* This has cond from encoding, required to be outside IT block. */
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if (a->cond >= 0xe) {
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return false;
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}
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if (s->condexec_mask) {
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unallocated_encoding(s);
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return true;
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}
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arm_skip_unless(s, a->cond);
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gen_jmp(s, read_pc(s) + a->imm);
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return true;
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}
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static bool trans_BL(DisasContext *s, arg_i *a)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_R[14], s->base.pc_next | s->thumb);
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gen_jmp(s, read_pc(s) + a->imm);
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return true;
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}
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static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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/* For A32, ARCH(5) is checked near the start of the uncond block. */
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if (s->thumb && (a->imm & 2)) {
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return false;
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}
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tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_R[14], s->base.pc_next | s->thumb);
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gen_bx_im(s, (read_pc(s) & ~3) + a->imm + !s->thumb);
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return true;
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}
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/*
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* Legacy decoder.
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*/
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@ -10371,7 +10424,7 @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a)
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static void disas_arm_insn(DisasContext *s, unsigned int insn)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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unsigned int cond, val, op1, i, rn;
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unsigned int cond, op1, i, rn;
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TCGv_i32 tmp;
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TCGv_i32 tmp2;
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TCGv_i32 addr;
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@ -10547,21 +10600,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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}
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gen_rfe(s, tmp, tmp2);
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return;
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} else if ((insn & 0x0e000000) == 0x0a000000) {
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/* branch link and change to thumb (blx <offset>) */
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int32_t offset;
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tmp = tcg_temp_new_i32(tcg_ctx);
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tcg_gen_movi_i32(tcg_ctx, tmp, s->base.pc_next);
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store_reg(s, 14, tmp);
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/* Sign-extend the 24-bit offset */
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offset = (((int32_t)insn) << 8) >> 8;
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val = read_pc(s);
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/* offset * 4 + bit24 * 2 + (thumb bit) */
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val += (offset << 2) | ((insn >> 23) & 2) | 1;
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/* protected by ARCH(5); above, near the start of uncond block */
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gen_bx_im(s, val);
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return;
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} else if ((insn & 0x0e000f00) == 0x0c000100) {
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if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
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/* iWMMXt register transfer. */
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@ -10655,23 +10693,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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case 0x7:
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case 0x08:
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case 0x09:
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/* All done in decodetree. Reach here for illegal ops. */
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goto illegal_op;
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case 0xa:
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case 0xb:
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{
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int32_t offset;
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/* branch (and link) */
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if (insn & (1 << 24)) {
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tmp = tcg_temp_new_i32(tcg_ctx);
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tcg_gen_movi_i32(tcg_ctx, tmp, s->base.pc_next);
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store_reg(s, 14, tmp);
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}
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offset = sextract32(insn << 2, 0, 26);
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gen_jmp(s, read_pc(s) + offset);
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}
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break;
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/* All done in decodetree. Reach here for illegal ops. */
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goto illegal_op;
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case 0xc:
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case 0xd:
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case 0xe:
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@ -11040,32 +11065,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
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if (insn & (1 << 15)) {
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/* Branches, misc control. */
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if (insn & 0x5000) {
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/* Unconditional branch. */
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/* signextend(hw1[10:0]) -> offset[:12]. */
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offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
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/* hw1[10:0] -> offset[11:1]. */
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offset |= (insn & 0x7ff) << 1;
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/* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
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offset[24:22] already have the same value because of the
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sign extension above. */
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offset ^= ((~insn) & (1 << 13)) << 10;
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offset ^= ((~insn) & (1 << 11)) << 11;
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if (insn & (1 << 14)) {
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/* Branch and link. */
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tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_R[14], s->base.pc_next | 1);
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}
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offset += read_pc(s);
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if (insn & (1 << 12)) {
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/* b/bl */
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gen_jmp(s, offset);
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} else {
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/* blx */
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offset &= ~(uint32_t)2;
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/* thumb2 bx, no need to check */
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gen_bx_im(s, offset);
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}
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/* Unconditional branch, in decodetree */
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goto illegal_op;
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} else if (((insn >> 23) & 7) == 7) {
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/* Misc control */
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if (insn & (1 << 13))
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@ -11151,24 +11152,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
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}
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}
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} else {
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/* Conditional branch. */
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op = (insn >> 22) & 0xf;
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/* Generate a conditional jump to next instruction. */
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arm_skip_unless(s, op);
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/* offset[11:1] = insn[10:0] */
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offset = (insn & 0x7ff) << 1;
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/* offset[17:12] = insn[21:16]. */
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offset |= (insn & 0x003f0000) >> 4;
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/* offset[31:20] = insn[26]. */
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offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
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/* offset[18] = insn[13]. */
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offset |= (insn & (1 << 13)) << 5;
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/* offset[19] = insn[11]. */
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offset |= (insn & (1 << 11)) << 8;
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/* jump to the offset */
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gen_jmp(s, read_pc(s) + offset);
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/* Conditional branch, in decodetree */
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goto illegal_op;
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}
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} else {
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/*
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