mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-05-04 19:52:07 +00:00
target-i386: emulate LOCK'ed cmpxchg using cmpxchg helpers
The diff here is uglier than necessary. All this does is to turn
FOO
into:
if (s->prefix & PREFIX_LOCK) {
BAR
} else {
FOO
}
where FOO is the original implementation of an unlocked cmpxchg.
Backports commit ae03f8de45427042ecd10b0941a005f21ecc064c from qemu
This commit is contained in:
Emilio G. Cota
Lioncash
parent
b48508a6c1
commit
a386368f82
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@ -76,8 +76,10 @@ DEF_HELPER_3(boundw, void, env, tl, int)
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DEF_HELPER_3(boundl, void, env, tl, int)
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DEF_HELPER_1(rsm, void, env)
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DEF_HELPER_2(into, void, env, int)
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DEF_HELPER_2(cmpxchg8b_unlocked, void, env, tl)
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DEF_HELPER_2(cmpxchg8b, void, env, tl)
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#ifdef TARGET_X86_64
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DEF_HELPER_2(cmpxchg16b_unlocked, void, env, tl)
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DEF_HELPER_2(cmpxchg16b, void, env, tl)
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#endif
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DEF_HELPER_1(single_step, void, env)
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@ -22,6 +22,8 @@
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#include "exec/helper-proto.h"
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#include "exec/exec-all.h"
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#include "exec/cpu_ldst.h"
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#include "qemu/int128.h"
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#include "tcg.h"
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#include "uc_priv.h"
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@ -35,53 +37,141 @@ void helper_unlock(CPUX86State *env)
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{
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}
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void helper_cmpxchg8b(CPUX86State *env, target_ulong a0)
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void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0)
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{
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uint64_t d;
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uintptr_t ra = GETPC();
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uint64_t oldv, cmpv, newv;
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int eflags;
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eflags = cpu_cc_compute_all(env, CC_OP);
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d = cpu_ldq_data_ra(env, a0, GETPC());
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if (d == (((uint64_t)env->regs[R_EDX] << 32) | (uint32_t)env->regs[R_EAX])) {
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cpu_stq_data_ra(env, a0, ((uint64_t)env->regs[R_ECX] << 32)
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| (uint32_t)env->regs[R_EBX], GETPC());
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cmpv = deposit64(env->regs[R_EAX], 32, 32, env->regs[R_EDX]);
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newv = deposit64(env->regs[R_EBX], 32, 32, env->regs[R_ECX]);
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oldv = cpu_ldq_data_ra(env, a0, ra);
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newv = (cmpv == oldv ? newv : oldv);
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/* always do the store */
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cpu_stq_data_ra(env, a0, newv, ra);
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if (oldv == cmpv) {
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eflags |= CC_Z;
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} else {
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/* always do the store */
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cpu_stq_data_ra(env, a0, d, GETPC());
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env->regs[R_EDX] = (uint32_t)(d >> 32);
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env->regs[R_EAX] = (uint32_t)d;
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env->regs[R_EAX] = (uint32_t)oldv;
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env->regs[R_EDX] = (uint32_t)(oldv >> 32);
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eflags &= ~CC_Z;
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}
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CC_SRC = eflags;
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}
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#ifdef TARGET_X86_64
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void helper_cmpxchg16b(CPUX86State *env, target_ulong a0)
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void helper_cmpxchg8b(CPUX86State *env, target_ulong a0)
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{
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uint64_t d0, d1;
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#ifdef CONFIG_ATOMIC64
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uint64_t oldv, cmpv, newv;
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int eflags;
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eflags = cpu_cc_compute_all(env, CC_OP);
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cmpv = deposit64(env->regs[R_EAX], 32, 32, env->regs[R_EDX]);
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newv = deposit64(env->regs[R_EBX], 32, 32, env->regs[R_ECX]);
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#ifdef CONFIG_USER_ONLY
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{
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uint64_t *haddr = g2h(a0);
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cmpv = cpu_to_le64(cmpv);
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newv = cpu_to_le64(newv);
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oldv = atomic_cmpxchg__nocheck(haddr, cmpv, newv);
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oldv = le64_to_cpu(oldv);
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}
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#else
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{
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uintptr_t ra = GETPC();
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int mem_idx = cpu_mmu_index(env, false);
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TCGMemOpIdx oi = make_memop_idx(MO_TEQ, mem_idx);
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oldv = helper_atomic_cmpxchgq_le_mmu(env, a0, cmpv, newv, oi, ra);
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}
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#endif
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if (oldv == cmpv) {
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eflags |= CC_Z;
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} else {
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env->regs[R_EAX] = (uint32_t)oldv;
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env->regs[R_EDX] = (uint32_t)(oldv >> 32);
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eflags &= ~CC_Z;
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}
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CC_SRC = eflags;
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#else
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cpu_loop_exit_atomic(ENV_GET_CPU(env), GETPC());
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#endif /* CONFIG_ATOMIC64 */
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}
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#ifdef TARGET_X86_64
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void helper_cmpxchg16b_unlocked(CPUX86State *env, target_ulong a0)
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{
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uintptr_t ra = GETPC();
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Int128 oldv, cmpv, newv;
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uint64_t o0, o1;
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int eflags;
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bool success;
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if ((a0 & 0xf) != 0) {
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raise_exception_ra(env, EXCP0D_GPF, GETPC());
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}
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eflags = cpu_cc_compute_all(env, CC_OP);
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d0 = cpu_ldq_data_ra(env, a0, GETPC());
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d1 = cpu_ldq_data_ra(env, a0 + 8, GETPC());
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if (d0 == env->regs[R_EAX] && d1 == env->regs[R_EDX]) {
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cpu_stq_data_ra(env, a0, env->regs[R_EBX], GETPC());
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cpu_stq_data_ra(env, a0 + 8, env->regs[R_ECX], GETPC());
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cmpv = int128_make128(env->regs[R_EAX], env->regs[R_EDX]);
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newv = int128_make128(env->regs[R_EBX], env->regs[R_ECX]);
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o0 = cpu_ldq_data_ra(env, a0 + 0, ra);
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o1 = cpu_ldq_data_ra(env, a0 + 8, ra);
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oldv = int128_make128(o0, o1);
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success = int128_eq(oldv, cmpv);
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if (!success) {
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newv = oldv;
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}
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cpu_stq_data_ra(env, a0 + 0, int128_getlo(newv), ra);
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cpu_stq_data_ra(env, a0 + 8, int128_gethi(newv), ra);
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if (success) {
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eflags |= CC_Z;
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} else {
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/* always do the store */
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cpu_stq_data_ra(env, a0, d0, GETPC());
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cpu_stq_data_ra(env, a0 + 8, d1, GETPC());
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env->regs[R_EDX] = d1;
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env->regs[R_EAX] = d0;
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env->regs[R_EAX] = int128_getlo(oldv);
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env->regs[R_EDX] = int128_gethi(oldv);
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eflags &= ~CC_Z;
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}
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CC_SRC = eflags;
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}
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void helper_cmpxchg16b(CPUX86State *env, target_ulong a0)
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{
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uintptr_t ra = GETPC();
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if ((a0 & 0xf) != 0) {
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raise_exception_ra(env, EXCP0D_GPF, ra);
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} else {
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#ifndef CONFIG_ATOMIC128
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cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
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#else
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int eflags = cpu_cc_compute_all(env, CC_OP);
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Int128 cmpv = int128_make128(env->regs[R_EAX], env->regs[R_EDX]);
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Int128 newv = int128_make128(env->regs[R_EBX], env->regs[R_ECX]);
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int mem_idx = cpu_mmu_index(env, false);
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TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
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Int128 oldv = helper_atomic_cmpxchgo_le_mmu(env, a0, cmpv,
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newv, oi, ra);
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if (int128_eq(oldv, cmpv)) {
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eflags |= CC_Z;
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} else {
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env->regs[R_EAX] = int128_getlo(oldv);
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env->regs[R_EDX] = int128_gethi(oldv);
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eflags &= ~CC_Z;
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}
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CC_SRC = eflags;
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#endif
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}
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}
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#endif
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void helper_boundw(CPUX86State *env, target_ulong a0, int v)
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@ -5721,57 +5721,57 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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case 0x1b0:
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case 0x1b1: /* cmpxchg Ev, Gv */
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{
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TCGLabel *label1, *label2;
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TCGv t0, t1, t2, a0;
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TCGv oldv, newv, cmpv;
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ot = mo_b_d(b, dflag);
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modrm = cpu_ldub_code(env, s->pc++);
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reg = ((modrm >> 3) & 7) | rex_r;
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mod = (modrm >> 6) & 3;
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t0 = tcg_temp_local_new(tcg_ctx);
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t1 = tcg_temp_local_new(tcg_ctx);
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t2 = tcg_temp_local_new(tcg_ctx);
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a0 = tcg_temp_local_new(tcg_ctx);
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gen_op_mov_v_reg(tcg_ctx, ot, t1, reg);
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if (mod == 3) {
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rm = (modrm & 7) | REX_B(s);
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gen_op_mov_v_reg(tcg_ctx, ot, t0, rm);
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oldv = tcg_temp_new(tcg_ctx);
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newv = tcg_temp_new(tcg_ctx);
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cmpv = tcg_temp_new(tcg_ctx);
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gen_op_mov_v_reg(tcg_ctx, ot, newv, reg);
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tcg_gen_mov_tl(tcg_ctx, cmpv, tcg_ctx->cpu_regs[R_EAX]);
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if (s->prefix & PREFIX_LOCK) {
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if (mod == 3) {
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goto illegal_op;
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}
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tcg_gen_atomic_cmpxchg_tl(tcg_ctx, oldv, cpu_A0, cmpv, newv,
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s->mem_index, ot | MO_LE);
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gen_op_mov_reg_v(tcg_ctx, ot, R_EAX, oldv);
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} else {
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gen_lea_modrm(env, s, modrm);
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tcg_gen_mov_tl(tcg_ctx, a0, cpu_A0);
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gen_op_ld_v(s, ot, t0, a0);
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rm = 0; /* avoid warning */
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if (mod == 3) {
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rm = (modrm & 7) | REX_B(s);
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gen_op_mov_v_reg(tcg_ctx, ot, oldv, rm);
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} else {
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gen_lea_modrm(env, s, modrm);
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gen_op_ld_v(s, ot, oldv, cpu_A0);
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rm = 0; /* avoid warning */
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}
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gen_extu(tcg_ctx, ot, oldv);
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gen_extu(tcg_ctx, ot, cmpv);
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/* store value = (old == cmp ? new : old); */
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tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, newv, oldv, cmpv, newv, oldv);
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if (mod == 3) {
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gen_op_mov_reg_v(tcg_ctx, ot, R_EAX, oldv);
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gen_op_mov_reg_v(tcg_ctx, ot, rm, newv);
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} else {
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/* Perform an unconditional store cycle like physical cpu;
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must be before changing accumulator to ensure
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idempotency if the store faults and the instruction
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is restarted */
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gen_op_st_v(s, ot, newv, cpu_A0);
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gen_op_mov_reg_v(tcg_ctx, ot, R_EAX, oldv);
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}
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}
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label1 = gen_new_label(tcg_ctx);
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tcg_gen_mov_tl(tcg_ctx, t2, cpu_regs[R_EAX]);
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gen_extu(tcg_ctx, ot, t0);
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gen_extu(tcg_ctx, ot, t2);
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tcg_gen_brcond_tl(tcg_ctx, TCG_COND_EQ, t2, t0, label1);
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label2 = gen_new_label(tcg_ctx);
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if (mod == 3) {
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gen_op_mov_reg_v(tcg_ctx, ot, R_EAX, t0);
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tcg_gen_br(tcg_ctx, label2);
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gen_set_label(tcg_ctx, label1);
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gen_op_mov_reg_v(tcg_ctx, ot, rm, t1);
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} else {
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/* perform no-op store cycle like physical cpu; must be
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before changing accumulator to ensure idempotency if
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the store faults and the instruction is restarted */
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gen_op_st_v(s, ot, t0, a0);
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gen_op_mov_reg_v(tcg_ctx, ot, R_EAX, t0);
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tcg_gen_br(tcg_ctx, label2);
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gen_set_label(tcg_ctx, label1);
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gen_op_st_v(s, ot, t1, a0);
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}
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gen_set_label(tcg_ctx, label2);
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tcg_gen_mov_tl(tcg_ctx, cpu_cc_src, t0);
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tcg_gen_mov_tl(tcg_ctx, cpu_cc_srcT, t2);
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tcg_gen_sub_tl(tcg_ctx, cpu_cc_dst, t2, t0);
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tcg_gen_mov_tl(tcg_ctx, cpu_cc_src, oldv);
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tcg_gen_mov_tl(tcg_ctx, cpu_cc_srcT, cmpv);
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tcg_gen_sub_tl(tcg_ctx, cpu_cc_dst, cmpv, oldv);
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set_cc_op(s, CC_OP_SUBB + ot);
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tcg_temp_free(tcg_ctx, t0);
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tcg_temp_free(tcg_ctx, t1);
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tcg_temp_free(tcg_ctx, t2);
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tcg_temp_free(tcg_ctx, a0);
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tcg_temp_free(tcg_ctx, oldv);
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tcg_temp_free(tcg_ctx, newv);
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tcg_temp_free(tcg_ctx, cmpv);
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}
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break;
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case 0x1c7: /* cmpxchg8b */
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@ -5784,14 +5784,22 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
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goto illegal_op;
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gen_lea_modrm(env, s, modrm);
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gen_helper_cmpxchg16b(tcg_ctx, cpu_env, cpu_A0);
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if ((s->prefix & PREFIX_LOCK) && tcg_ctx->uc->parallel_cpus) {
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gen_helper_cmpxchg16b(tcg_ctx, cpu_env, cpu_A0);
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} else {
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gen_helper_cmpxchg16b_unlocked(tcg_ctx, cpu_env, cpu_A0);
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}
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} else
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#endif
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{
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if (!(s->cpuid_features & CPUID_CX8))
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goto illegal_op;
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gen_lea_modrm(env, s, modrm);
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gen_helper_cmpxchg8b(tcg_ctx, cpu_env, cpu_A0);
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if ((s->prefix & PREFIX_LOCK) && tcg_ctx->uc->parallel_cpus) {
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gen_helper_cmpxchg8b(tcg_ctx, cpu_env, cpu_A0);
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} else {
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gen_helper_cmpxchg8b_unlocked(tcg_ctx, cpu_env, cpu_A0);
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}
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}
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set_cc_op(s, CC_OP_EFLAGS);
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break;
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