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tcg/aarch64: Make direct jump patching thread-safe
Ensure direct jump patching in AArch64 is atomic by using atomic_read()/atomic_set() for code patching. Backports commit 9e269112953be4d670cb0d25042bd6546fcf3e45 from qemu
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@ -77,6 +77,18 @@ static inline void reloc_pc26(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
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*code_ptr = deposit32(*code_ptr, 0, 26, offset);
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}
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static inline void reloc_pc26_atomic(tcg_insn_unit *code_ptr,
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tcg_insn_unit *target)
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{
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ptrdiff_t offset = target - code_ptr;
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tcg_insn_unit insn;
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tcg_debug_assert(offset == sextract64(offset, 0, 26));
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/* read instruction, mask away previous PC_REL26 parameter contents,
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set the proper offset, then write back the instruction. */
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insn = atomic_read(code_ptr);
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atomic_set(code_ptr, deposit32(insn, 0, 26, offset));
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}
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static inline void reloc_pc19(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
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{
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ptrdiff_t offset = target - code_ptr;
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@ -839,7 +851,7 @@ void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr)
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tcg_insn_unit *code_ptr = (tcg_insn_unit *)jmp_addr;
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tcg_insn_unit *target = (tcg_insn_unit *)addr;
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reloc_pc26(code_ptr, target);
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reloc_pc26_atomic(code_ptr, target);
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flush_icache_range(jmp_addr, jmp_addr + 4);
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}
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