yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-06-02 01:40:17 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/arm: Add predicate registers for SVE

Browse source 
Backports commit 3c7d30866fd1f56e5945726221410e0d8d535033 from qemu
This commit is contained in:
Richard Henderson 2018-03-07 11:34:52 -05:00 committed by Lioncash
parent 834e3a1d04
commit a47fb718bc
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 12 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
qemu/target/arm/cpu.h
View file

@ -193,6 +193,13 @@ typedef struct ARMVectorReg {
uint64_t QEMU_ALIGNED(16, d[2 * ARM_MAX_VQ]); uint64_t QEMU_ALIGNED(16, d[2 * ARM_MAX_VQ]);
} ARMVectorReg; } ARMVectorReg;
/* In AArch32 mode, predicate registers do not exist at all. */
#ifdef TARGET_AARCH64
typedef struct ARMPredicateReg {
uint64_t QEMU_ALIGNED(16, p[2 * ARM_MAX_VQ / 8]);
} ARMPredicateReg;
#endif
typedef struct CPUARMState { typedef struct CPUARMState {
/* Regs for current mode. */ /* Regs for current mode. */
uint32_t regs[16]; uint32_t regs[16];
@ -519,6 +526,11 @@ typedef struct CPUARMState {
struct { struct {
ARMVectorReg zregs[32]; ARMVectorReg zregs[32];
#ifdef TARGET_AARCH64
/* Store FFR as pregs[16] to make it easier to treat as any other. */
ARMPredicateReg pregs[17];
#endif
uint32_t xregs[16]; uint32_t xregs[16];
/* We store these fpcsr fields separately for convenience. */ /* We store these fpcsr fields separately for convenience. */
int vec_len; int vec_len;