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target/mips: Add CP0 PWSize register

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Add PWSize register (CP0 Register 5, Select 7).

The PWSize register configures hardware page table walking for TLB
refills.

This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:

BDW (37..32) Base Directory index width (MIPS64 only)
GDW (29..24) Global Directory index width
UDW (23..18) Upper Directory index width
MDW (17..12) Middle Directory index width
PTW (11..6 ) Page Table index width
PTEW ( 5..0 ) Left shift applied to the Page Table index

Backports commit 20b28ebc49945583d7191b57755cfd92433de9ff from qemu
This commit is contained in:
Yongbok Kim 2018-10-23 14:08:44 -04:00 committed by Lioncash
parent 0597704314
commit a5194f6dfc
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
9 changed files with 45 additions and 0 deletions
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1
qemu/header_gen.py
View file

@ -4935,6 +4935,7 @@ mips_symbols = (
'helper_mtc0_pagemask',
'helper_mtc0_performance0',
'helper_mtc0_pwfield',
'helper_mtc0_pwsize',
'helper_mtc0_segctl0',
'helper_mtc0_segctl1',
'helper_mtc0_segctl2',

1
qemu/mips.h
View file

@ -3909,6 +3909,7 @@
#define helper_mtc0_pagemask helper_mtc0_pagemask_mips
#define helper_mtc0_performance0 helper_mtc0_performance0_mips
#define helper_mtc0_pwfield helper_mtc0_pwfield_mips
#define helper_mtc0_pwsize helper_mtc0_pwsize_mips
#define helper_mtc0_segctl0 helper_mtc0_segctl0_mips
#define helper_mtc0_segctl1 helper_mtc0_segctl1_mips
#define helper_mtc0_segctl2 helper_mtc0_segctl2_mips

1
qemu/mips64.h
View file

@ -3909,6 +3909,7 @@
#define helper_mtc0_pagemask helper_mtc0_pagemask_mips64
#define helper_mtc0_performance0 helper_mtc0_performance0_mips64
#define helper_mtc0_pwfield helper_mtc0_pwfield_mips64
#define helper_mtc0_pwsize helper_mtc0_pwsize_mips64
#define helper_mtc0_segctl0 helper_mtc0_segctl0_mips64
#define helper_mtc0_segctl1 helper_mtc0_segctl1_mips64
#define helper_mtc0_segctl2 helper_mtc0_segctl2_mips64

1
qemu/mips64el.h
View file

@ -3909,6 +3909,7 @@
#define helper_mtc0_pagemask helper_mtc0_pagemask_mips64el
#define helper_mtc0_performance0 helper_mtc0_performance0_mips64el
#define helper_mtc0_pwfield helper_mtc0_pwfield_mips64el
#define helper_mtc0_pwsize helper_mtc0_pwsize_mips64el
#define helper_mtc0_segctl0 helper_mtc0_segctl0_mips64el
#define helper_mtc0_segctl1 helper_mtc0_segctl1_mips64el
#define helper_mtc0_segctl2 helper_mtc0_segctl2_mips64el

1
qemu/mipsel.h
View file

@ -3909,6 +3909,7 @@
#define helper_mtc0_pagemask helper_mtc0_pagemask_mipsel
#define helper_mtc0_performance0 helper_mtc0_performance0_mipsel
#define helper_mtc0_pwfield helper_mtc0_pwfield_mipsel
#define helper_mtc0_pwsize helper_mtc0_pwsize_mipsel
#define helper_mtc0_segctl0 helper_mtc0_segctl0_mipsel
#define helper_mtc0_segctl1 helper_mtc0_segctl1_mipsel
#define helper_mtc0_segctl2 helper_mtc0_segctl2_mipsel

10
qemu/target/mips/cpu.h
View file

@ -433,6 +433,16 @@ struct CPUMIPSState {
#define CP0PF_PTW 6 /* 11..6 */
#define CP0PF_PTEW 0 /* 5..0 */
#endif
target_ulong CP0_PWSize;
#if defined(TARGET_MIPS64)
#define CP0PS_BDW 32 /* 37..32 */
#endif
#define CP0PS_PS 30
#define CP0PS_GDW 24 /* 29..24 */
#define CP0PS_UDW 18 /* 23..18 */
#define CP0PS_MDW 12 /* 17..12 */
#define CP0PS_PTW 6 /* 11..6 */
#define CP0PS_PTEW 0 /* 5..0 */
/*
* CP0 Register 6
*/

1
qemu/target/mips/helper.h
View file

@ -121,6 +121,7 @@ DEF_HELPER_2(mtc0_segctl0, void, env, tl)
DEF_HELPER_2(mtc0_segctl1, void, env, tl)
DEF_HELPER_2(mtc0_segctl2, void, env, tl)
DEF_HELPER_2(mtc0_pwfield, void, env, tl)
DEF_HELPER_2(mtc0_pwsize, void, env, tl)
DEF_HELPER_2(mtc0_wired, void, env, tl)
DEF_HELPER_2(mtc0_srsconf0, void, env, tl)
DEF_HELPER_2(mtc0_srsconf1, void, env, tl)

9
qemu/target/mips/op_helper.c
View file

@ -1497,6 +1497,15 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
#endif
}
void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1)
{
#if defined(TARGET_MIPS64)
env->CP0_PWSize = arg1 & 0x3F7FFFFFFFULL;
#else
env->CP0_PWSize = arg1 & 0x3FFFFFFF;
#endif
}
void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
{
if (env->insn_flags & ISA_MIPS32R6) {

20
qemu/target/mips/translate.c
View file

@ -6200,6 +6200,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PWField));
rn = "PWField";
break;
case 7:
check_pw(ctx);
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PWSize));
rn = "PWSize";
break;
default:
goto cp0_unimplemented;
}
@ -6907,6 +6912,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_pwfield(tcg_ctx, tcg_ctx->cpu_env, arg);
rn = "PWField";
break;
case 7:
check_pw(ctx);
gen_helper_mtc0_pwsize(tcg_ctx, tcg_ctx->cpu_env, arg);
rn = "PWSize";
break;
default:
goto cp0_unimplemented;
}
@ -7624,6 +7634,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_PWField));
rn = "PWField";
break;
case 7:
check_pw(ctx);
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_PWSize));
rn = "PWSize";
break;
default:
goto cp0_unimplemented;
}
@ -8313,6 +8328,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_pwfield(tcg_ctx, tcg_ctx->cpu_env, arg);
rn = "PWField";
break;
case 7:
check_pw(ctx);
gen_helper_mtc0_pwsize(tcg_ctx, tcg_ctx->cpu_env, arg);
rn = "PWSize";
break;
default:
goto cp0_unimplemented;
}