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target-m68k: Replace helper_xflag_lt with setcond
Backports commit f9083519034aaa5ad5cd2c5727bd61c29bf60bc5 from qemu
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b079255576
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@ -378,11 +378,6 @@ uint32_t HELPER(addx_cc)(CPUM68KState *env, uint32_t op1, uint32_t op2)
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return res;
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}
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uint32_t HELPER(xflag_lt)(uint32_t a, uint32_t b)
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{
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return a < b;
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}
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void HELPER(set_sr)(CPUM68KState *env, uint32_t val)
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{
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env->sr = val & 0xffff;
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@ -10,7 +10,6 @@ DEF_HELPER_3(subx_cc, i32, env, i32, i32)
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DEF_HELPER_3(shl_cc, i32, env, i32, i32)
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DEF_HELPER_3(shr_cc, i32, env, i32, i32)
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DEF_HELPER_3(sar_cc, i32, env, i32, i32)
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DEF_HELPER_2(xflag_lt, i32, i32, i32)
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DEF_HELPER_2(set_sr, void, env, i32)
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DEF_HELPER_3(movec, void, env, i32, i32)
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@ -1029,10 +1029,10 @@ DISAS_INSN(addsub)
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}
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if (add) {
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tcg_gen_add_i32(tcg_ctx, dest, tmp, src);
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gen_helper_xflag_lt(tcg_ctx, tcg_ctx->QREG_CC_X, dest, src);
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tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, dest, src);
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s->cc_op = CC_OP_ADD;
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} else {
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gen_helper_xflag_lt(tcg_ctx, tcg_ctx->QREG_CC_X, tmp, src);
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tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, tmp, src);
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tcg_gen_sub_i32(tcg_ctx, dest, tmp, src);
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s->cc_op = CC_OP_SUB;
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}
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@ -1252,7 +1252,7 @@ DISAS_INSN(arith_im)
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break;
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case 2: /* subi */
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tcg_gen_mov_i32(tcg_ctx, dest, src1);
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gen_helper_xflag_lt(tcg_ctx, tcg_ctx->QREG_CC_X, dest, tcg_const_i32(tcg_ctx, im));
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tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, dest, tcg_const_i32(tcg_ctx, im));
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tcg_gen_subi_i32(tcg_ctx, dest, dest, im);
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gen_update_cc_add(s, dest, tcg_const_i32(tcg_ctx, im));
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s->cc_op = CC_OP_SUB;
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@ -1261,7 +1261,7 @@ DISAS_INSN(arith_im)
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tcg_gen_mov_i32(tcg_ctx, dest, src1);
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tcg_gen_addi_i32(tcg_ctx, dest, dest, im);
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gen_update_cc_add(s, dest, tcg_const_i32(tcg_ctx, im));
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gen_helper_xflag_lt(tcg_ctx, tcg_ctx->QREG_CC_X, dest, tcg_const_i32(tcg_ctx, im));
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tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, dest, tcg_const_i32(tcg_ctx, im));
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s->cc_op = CC_OP_ADD;
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break;
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case 5: /* eori */
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@ -1399,7 +1399,7 @@ DISAS_INSN(neg)
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tcg_gen_neg_i32(tcg_ctx, reg, src1);
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s->cc_op = CC_OP_SUB;
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gen_update_cc_add(s, reg, src1);
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gen_helper_xflag_lt(tcg_ctx, tcg_ctx->QREG_CC_X, tcg_const_i32(tcg_ctx, 0), src1);
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tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, tcg_const_i32(tcg_ctx, 0), src1);
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s->cc_op = CC_OP_SUB;
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}
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@ -1659,12 +1659,12 @@ DISAS_INSN(addsubq)
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} else {
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src2 = tcg_const_i32(tcg_ctx, val);
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if (insn & 0x0100) {
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gen_helper_xflag_lt(tcg_ctx, tcg_ctx->QREG_CC_X, dest, src2);
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tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, dest, src2);
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tcg_gen_subi_i32(tcg_ctx, dest, dest, val);
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s->cc_op = CC_OP_SUB;
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} else {
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tcg_gen_addi_i32(tcg_ctx, dest, dest, val);
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gen_helper_xflag_lt(tcg_ctx, tcg_ctx->QREG_CC_X, dest, src2);
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tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, dest, src2);
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s->cc_op = CC_OP_ADD;
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}
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gen_update_cc_add(s, dest, src2);
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