tcg: Remove gen_intermediate_code_pc

It is no longer used, so tidy up everything reached by it.
This includes the gen_opc_* arrays, the search_pc parameter
and the inline gen_intermediate_code_internal functions.

Backports commit 4e5e1215156662b2b153255c49d4640d82c5568b from qemu

qemu/aarch64.h

@@ -147,7 +147,6 @@
 #define arm_free_cc arm_free_cc_aarch64
 #define arm_generate_debug_exceptions arm_generate_debug_exceptions_aarch64
 #define gen_intermediate_code gen_intermediate_code_aarch64
-#define gen_intermediate_code_pc gen_intermediate_code_pc_aarch64
 #define arm_gen_test_cc arm_gen_test_cc_aarch64
 #define arm_gt_ptimer_cb arm_gt_ptimer_cb_aarch64
 #define arm_gt_vtimer_cb arm_gt_vtimer_cb_aarch64
@@ -1141,8 +1140,8 @@
 #define gen_helper_wfi gen_helper_wfi_aarch64
 #define gen_helper_yield gen_helper_yield_aarch64
 #define gen_hvc gen_hvc_aarch64
-#define gen_intermediate_code_internal gen_intermediate_code_internal_aarch64
+#define gen_intermediate_code gen_intermediate_code_aarch64
-#define gen_intermediate_code_internal_a64 gen_intermediate_code_internal_a64_aarch64
+#define gen_intermediate_code_a64 gen_intermediate_code_a64_aarch64
 #define gen_iwmmxt_address gen_iwmmxt_address_aarch64
 #define gen_iwmmxt_shift gen_iwmmxt_shift_aarch64
 #define gen_jmp gen_jmp_aarch64

qemu/aarch64eb.h

@@ -147,7 +147,6 @@
 #define arm_free_cc arm_free_cc_aarch64eb
 #define arm_generate_debug_exceptions arm_generate_debug_exceptions_aarch64eb
 #define gen_intermediate_code gen_intermediate_code_aarch64eb
-#define gen_intermediate_code_pc gen_intermediate_code_pc_aarch64eb
 #define arm_gen_test_cc arm_gen_test_cc_aarch64eb
 #define arm_gt_ptimer_cb arm_gt_ptimer_cb_aarch64eb
 #define arm_gt_vtimer_cb arm_gt_vtimer_cb_aarch64eb
@@ -1141,8 +1140,8 @@
 #define gen_helper_wfi gen_helper_wfi_aarch64eb
 #define gen_helper_yield gen_helper_yield_aarch64eb
 #define gen_hvc gen_hvc_aarch64eb
-#define gen_intermediate_code_internal gen_intermediate_code_internal_aarch64eb
+#define gen_intermediate_code gen_intermediate_code_aarch64eb
-#define gen_intermediate_code_internal_a64 gen_intermediate_code_internal_a64_aarch64eb
+#define gen_intermediate_code_a64 gen_intermediate_code_a64_aarch64eb
 #define gen_iwmmxt_address gen_iwmmxt_address_aarch64eb
 #define gen_iwmmxt_shift gen_iwmmxt_shift_aarch64eb
 #define gen_jmp gen_jmp_aarch64eb

qemu/arm.h

@@ -147,7 +147,6 @@
 #define arm_free_cc arm_free_cc_arm
 #define arm_generate_debug_exceptions arm_generate_debug_exceptions_arm
 #define gen_intermediate_code gen_intermediate_code_arm
-#define gen_intermediate_code_pc gen_intermediate_code_pc_arm
 #define arm_gen_test_cc arm_gen_test_cc_arm
 #define arm_gt_ptimer_cb arm_gt_ptimer_cb_arm
 #define arm_gt_vtimer_cb arm_gt_vtimer_cb_arm
@@ -1141,8 +1140,8 @@
 #define gen_helper_wfi gen_helper_wfi_arm
 #define gen_helper_yield gen_helper_yield_arm
 #define gen_hvc gen_hvc_arm
-#define gen_intermediate_code_internal gen_intermediate_code_internal_arm
+#define gen_intermediate_code gen_intermediate_code_arm
-#define gen_intermediate_code_internal_a64 gen_intermediate_code_internal_a64_arm
+#define gen_intermediate_code_a64 gen_intermediate_code_a64_arm
 #define gen_iwmmxt_address gen_iwmmxt_address_arm
 #define gen_iwmmxt_shift gen_iwmmxt_shift_arm
 #define gen_jmp gen_jmp_arm

qemu/armeb.h

@@ -147,7 +147,6 @@
 #define arm_free_cc arm_free_cc_armeb
 #define arm_generate_debug_exceptions arm_generate_debug_exceptions_armeb
 #define gen_intermediate_code gen_intermediate_code_armeb
-#define gen_intermediate_code_pc gen_intermediate_code_pc_armeb
 #define arm_gen_test_cc arm_gen_test_cc_armeb
 #define arm_gt_ptimer_cb arm_gt_ptimer_cb_armeb
 #define arm_gt_vtimer_cb arm_gt_vtimer_cb_armeb
@@ -1141,8 +1140,8 @@
 #define gen_helper_wfi gen_helper_wfi_armeb
 #define gen_helper_yield gen_helper_yield_armeb
 #define gen_hvc gen_hvc_armeb
-#define gen_intermediate_code_internal gen_intermediate_code_internal_armeb
+#define gen_intermediate_code gen_intermediate_code_armeb
-#define gen_intermediate_code_internal_a64 gen_intermediate_code_internal_a64_armeb
+#define gen_intermediate_code_a64 gen_intermediate_code_a64_armeb
 #define gen_iwmmxt_address gen_iwmmxt_address_armeb
 #define gen_iwmmxt_shift gen_iwmmxt_shift_armeb
 #define gen_jmp gen_jmp_armeb

qemu/header_gen.py

@@ -153,7 +153,6 @@ symbols = (
     'arm_free_cc',
     'arm_generate_debug_exceptions',
     'gen_intermediate_code',
-    'gen_intermediate_code_pc',
     'arm_gen_test_cc',
     'arm_gt_ptimer_cb',
     'arm_gt_vtimer_cb',
@@ -1147,8 +1146,8 @@ symbols = (
     'gen_helper_wfi',
     'gen_helper_yield',
     'gen_hvc',
-    'gen_intermediate_code_internal',
+    'gen_intermediate_code',
-    'gen_intermediate_code_internal_a64',
+    'gen_intermediate_code_a64',
     'gen_iwmmxt_address',
     'gen_iwmmxt_shift',
     'gen_jmp',

qemu/include/exec/exec-all.h

@@ -72,7 +72,6 @@ typedef struct TranslationBlock TranslationBlock;
 #include "qemu/log.h"
 
 void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
-void gen_intermediate_code_pc(CPUArchState *env, struct TranslationBlock *tb);
 void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
                           target_ulong *data);
 bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);

qemu/m68k.h

@@ -147,7 +147,6 @@
 #define arm_free_cc arm_free_cc_m68k
 #define arm_generate_debug_exceptions arm_generate_debug_exceptions_m68k
 #define gen_intermediate_code gen_intermediate_code_m68k
-#define gen_intermediate_code_pc gen_intermediate_code_pc_m68k
 #define arm_gen_test_cc arm_gen_test_cc_m68k
 #define arm_gt_ptimer_cb arm_gt_ptimer_cb_m68k
 #define arm_gt_vtimer_cb arm_gt_vtimer_cb_m68k
@@ -1141,8 +1140,8 @@
 #define gen_helper_wfi gen_helper_wfi_m68k
 #define gen_helper_yield gen_helper_yield_m68k
 #define gen_hvc gen_hvc_m68k
-#define gen_intermediate_code_internal gen_intermediate_code_internal_m68k
+#define gen_intermediate_code gen_intermediate_code_m68k
-#define gen_intermediate_code_internal_a64 gen_intermediate_code_internal_a64_m68k
+#define gen_intermediate_code_a64 gen_intermediate_code_a64_m68k
 #define gen_iwmmxt_address gen_iwmmxt_address_m68k
 #define gen_iwmmxt_shift gen_iwmmxt_shift_m68k
 #define gen_jmp gen_jmp_m68k

qemu/mips.h

@@ -147,7 +147,6 @@
 #define arm_free_cc arm_free_cc_mips
 #define arm_generate_debug_exceptions arm_generate_debug_exceptions_mips
 #define gen_intermediate_code gen_intermediate_code_mips
-#define gen_intermediate_code_pc gen_intermediate_code_pc_mips
 #define arm_gen_test_cc arm_gen_test_cc_mips
 #define arm_gt_ptimer_cb arm_gt_ptimer_cb_mips
 #define arm_gt_vtimer_cb arm_gt_vtimer_cb_mips
@@ -1141,8 +1140,8 @@
 #define gen_helper_wfi gen_helper_wfi_mips
 #define gen_helper_yield gen_helper_yield_mips
 #define gen_hvc gen_hvc_mips
-#define gen_intermediate_code_internal gen_intermediate_code_internal_mips
+#define gen_intermediate_code gen_intermediate_code_mips
-#define gen_intermediate_code_internal_a64 gen_intermediate_code_internal_a64_mips
+#define gen_intermediate_code_a64 gen_intermediate_code_a64_mips
 #define gen_iwmmxt_address gen_iwmmxt_address_mips
 #define gen_iwmmxt_shift gen_iwmmxt_shift_mips
 #define gen_jmp gen_jmp_mips

qemu/mips64.h

@@ -147,7 +147,6 @@
 #define arm_free_cc arm_free_cc_mips64
 #define arm_generate_debug_exceptions arm_generate_debug_exceptions_mips64
 #define gen_intermediate_code gen_intermediate_code_mips64
-#define gen_intermediate_code_pc gen_intermediate_code_pc_mips64
 #define arm_gen_test_cc arm_gen_test_cc_mips64
 #define arm_gt_ptimer_cb arm_gt_ptimer_cb_mips64
 #define arm_gt_vtimer_cb arm_gt_vtimer_cb_mips64
@@ -1141,8 +1140,8 @@
 #define gen_helper_wfi gen_helper_wfi_mips64
 #define gen_helper_yield gen_helper_yield_mips64
 #define gen_hvc gen_hvc_mips64
-#define gen_intermediate_code_internal gen_intermediate_code_internal_mips64
+#define gen_intermediate_code gen_intermediate_code_mips64
-#define gen_intermediate_code_internal_a64 gen_intermediate_code_internal_a64_mips64
+#define gen_intermediate_code_a64 gen_intermediate_code_a64_mips64
 #define gen_iwmmxt_address gen_iwmmxt_address_mips64
 #define gen_iwmmxt_shift gen_iwmmxt_shift_mips64
 #define gen_jmp gen_jmp_mips64

qemu/mips64el.h

@@ -147,7 +147,6 @@
 #define arm_free_cc arm_free_cc_mips64el
 #define arm_generate_debug_exceptions arm_generate_debug_exceptions_mips64el
 #define gen_intermediate_code gen_intermediate_code_mips64el
-#define gen_intermediate_code_pc gen_intermediate_code_pc_mips64el
 #define arm_gen_test_cc arm_gen_test_cc_mips64el
 #define arm_gt_ptimer_cb arm_gt_ptimer_cb_mips64el
 #define arm_gt_vtimer_cb arm_gt_vtimer_cb_mips64el
@@ -1141,8 +1140,8 @@
 #define gen_helper_wfi gen_helper_wfi_mips64el
 #define gen_helper_yield gen_helper_yield_mips64el
 #define gen_hvc gen_hvc_mips64el
-#define gen_intermediate_code_internal gen_intermediate_code_internal_mips64el
+#define gen_intermediate_code gen_intermediate_code_mips64el
-#define gen_intermediate_code_internal_a64 gen_intermediate_code_internal_a64_mips64el
+#define gen_intermediate_code_a64 gen_intermediate_code_a64_mips64el
 #define gen_iwmmxt_address gen_iwmmxt_address_mips64el
 #define gen_iwmmxt_shift gen_iwmmxt_shift_mips64el
 #define gen_jmp gen_jmp_mips64el

qemu/mipsel.h

@@ -147,7 +147,6 @@
 #define arm_free_cc arm_free_cc_mipsel
 #define arm_generate_debug_exceptions arm_generate_debug_exceptions_mipsel
 #define gen_intermediate_code gen_intermediate_code_mipsel
-#define gen_intermediate_code_pc gen_intermediate_code_pc_mipsel
 #define arm_gen_test_cc arm_gen_test_cc_mipsel
 #define arm_gt_ptimer_cb arm_gt_ptimer_cb_mipsel
 #define arm_gt_vtimer_cb arm_gt_vtimer_cb_mipsel
@@ -1141,8 +1140,8 @@
 #define gen_helper_wfi gen_helper_wfi_mipsel
 #define gen_helper_yield gen_helper_yield_mipsel
 #define gen_hvc gen_hvc_mipsel
-#define gen_intermediate_code_internal gen_intermediate_code_internal_mipsel
+#define gen_intermediate_code gen_intermediate_code_mipsel
-#define gen_intermediate_code_internal_a64 gen_intermediate_code_internal_a64_mipsel
+#define gen_intermediate_code_a64 gen_intermediate_code_a64_mipsel
 #define gen_iwmmxt_address gen_iwmmxt_address_mipsel
 #define gen_iwmmxt_shift gen_iwmmxt_shift_mipsel
 #define gen_jmp gen_jmp_mipsel

qemu/powerpc.h

@@ -147,7 +147,6 @@
 #define arm_free_cc arm_free_cc_powerpc
 #define arm_generate_debug_exceptions arm_generate_debug_exceptions_powerpc
 #define gen_intermediate_code gen_intermediate_code_powerpc
-#define gen_intermediate_code_pc gen_intermediate_code_pc_powerpc
 #define arm_gen_test_cc arm_gen_test_cc_powerpc
 #define arm_gt_ptimer_cb arm_gt_ptimer_cb_powerpc
 #define arm_gt_vtimer_cb arm_gt_vtimer_cb_powerpc
@@ -1141,8 +1140,8 @@
 #define gen_helper_wfi gen_helper_wfi_powerpc
 #define gen_helper_yield gen_helper_yield_powerpc
 #define gen_hvc gen_hvc_powerpc
-#define gen_intermediate_code_internal gen_intermediate_code_internal_powerpc
+#define gen_intermediate_code gen_intermediate_code_powerpc
-#define gen_intermediate_code_internal_a64 gen_intermediate_code_internal_a64_powerpc
+#define gen_intermediate_code_a64 gen_intermediate_code_a64_powerpc
 #define gen_iwmmxt_address gen_iwmmxt_address_powerpc
 #define gen_iwmmxt_shift gen_iwmmxt_shift_powerpc
 #define gen_jmp gen_jmp_powerpc

qemu/sparc.h

@@ -147,7 +147,6 @@
 #define arm_free_cc arm_free_cc_sparc
 #define arm_generate_debug_exceptions arm_generate_debug_exceptions_sparc
 #define gen_intermediate_code gen_intermediate_code_sparc
-#define gen_intermediate_code_pc gen_intermediate_code_pc_sparc
 #define arm_gen_test_cc arm_gen_test_cc_sparc
 #define arm_gt_ptimer_cb arm_gt_ptimer_cb_sparc
 #define arm_gt_vtimer_cb arm_gt_vtimer_cb_sparc
@@ -1141,8 +1140,8 @@
 #define gen_helper_wfi gen_helper_wfi_sparc
 #define gen_helper_yield gen_helper_yield_sparc
 #define gen_hvc gen_hvc_sparc
-#define gen_intermediate_code_internal gen_intermediate_code_internal_sparc
+#define gen_intermediate_code gen_intermediate_code_sparc
-#define gen_intermediate_code_internal_a64 gen_intermediate_code_internal_a64_sparc
+#define gen_intermediate_code_a64 gen_intermediate_code_a64_sparc
 #define gen_iwmmxt_address gen_iwmmxt_address_sparc
 #define gen_iwmmxt_shift gen_iwmmxt_shift_sparc
 #define gen_jmp gen_jmp_sparc

qemu/sparc64.h

@@ -147,7 +147,6 @@
 #define arm_free_cc arm_free_cc_sparc64
 #define arm_generate_debug_exceptions arm_generate_debug_exceptions_sparc64
 #define gen_intermediate_code gen_intermediate_code_sparc64
-#define gen_intermediate_code_pc gen_intermediate_code_pc_sparc64
 #define arm_gen_test_cc arm_gen_test_cc_sparc64
 #define arm_gt_ptimer_cb arm_gt_ptimer_cb_sparc64
 #define arm_gt_vtimer_cb arm_gt_vtimer_cb_sparc64
@@ -1141,8 +1140,8 @@
 #define gen_helper_wfi gen_helper_wfi_sparc64
 #define gen_helper_yield gen_helper_yield_sparc64
 #define gen_hvc gen_hvc_sparc64
-#define gen_intermediate_code_internal gen_intermediate_code_internal_sparc64
+#define gen_intermediate_code gen_intermediate_code_sparc64
-#define gen_intermediate_code_internal_a64 gen_intermediate_code_internal_a64_sparc64
+#define gen_intermediate_code_a64 gen_intermediate_code_a64_sparc64
 #define gen_iwmmxt_address gen_iwmmxt_address_sparc64
 #define gen_iwmmxt_shift gen_iwmmxt_shift_sparc64
 #define gen_jmp gen_jmp_sparc64

qemu/target-arm/translate-a64.c

@@ -11205,15 +11205,12 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
     free_tmp_a64(s);
 }
 
-void gen_intermediate_code_internal_a64(ARMCPU *cpu,
+void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
-                                        TranslationBlock *tb,
-                                        bool search_pc)
 {
     CPUState *cs = CPU(cpu);
     CPUARMState *env = &cpu->env;
     DisasContext dc1, *dc = &dc1;
     CPUBreakpoint *bp;
-    int j, lj;
     target_ulong pc_start;
     target_ulong next_page_start;
     int num_insns;
@@ -11279,7 +11276,6 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
     init_tmp_a64_array(dc);
 
     next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
-    lj = -1;
     num_insns = 0;
     max_insns = tb->cflags & CF_COUNT_MASK;
     if (max_insns == 0) {
@@ -11326,18 +11322,6 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
             }
         }
 
-        if (search_pc) {
-            j = tcg_op_buf_count(tcg_ctx);
-            if (lj < j) {
-                lj++;
-                while (lj < j) {
-                    tcg_ctx->gen_opc_instr_start[lj++] = 0;
-                }
-            }
-            tcg_ctx->gen_opc_pc[lj] = dc->pc;
-            tcg_ctx->gen_opc_instr_start[lj] = 1;
-            //tcg_ctx->gen_opc_icount[lj] = num_insns;
-        }
         tcg_gen_insn_start(tcg_ctx, dc->pc, 0);
         num_insns++;
 
@@ -11449,16 +11433,8 @@ tb_end:
 done_generating:
     gen_tb_end(tcg_ctx, tb, num_insns);
 
-    if (search_pc) {
-        j = tcg_op_buf_count(tcg_ctx);
-        lj++;
-        while (lj <= j) {
-            tcg_ctx->gen_opc_instr_start[lj++] = 0;
-        }
-    } else {
     tb->size = dc->pc - pc_start;
     tb->icount = num_insns;
-    }
 
     env->uc->block_full = block_full;
 }

qemu/target-arm/translate.c

@@ -11338,17 +11338,13 @@ undef:
 }
 
 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
-   basic block 'tb'. If search_pc is TRUE, also generate PC
+   basic block 'tb'.  */
-   information for each intermediate instruction. */
+void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
-static inline void gen_intermediate_code_internal(ARMCPU *cpu,
-                                                  TranslationBlock *tb,
-                                                  bool search_pc)
 {
+    ARMCPU *cpu = arm_env_get_cpu(env);
     CPUState *cs = CPU(cpu);
-    CPUARMState *env = &cpu->env;
     DisasContext dc1, *dc = &dc1;
     CPUBreakpoint *bp;
-    int j, lj;
     target_ulong pc_start;
     target_ulong next_page_start;
     int num_insns;
@@ -11362,7 +11358,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
      * the A32/T32 complexity to do with conditional execution/IT blocks/etc.
      */
     if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
-        gen_intermediate_code_internal_a64(cpu, tb, search_pc);
+        gen_intermediate_code_a64(cpu, tb);
         return;
     }
 
@@ -11430,7 +11426,6 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
     /* FIXME: tcg_ctx->cpu_M0 can probably be the same as tcg_ctx->cpu_V0.  */
     tcg_ctx->cpu_M0 = tcg_temp_new_i64(tcg_ctx);
     next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
-    lj = -1;
     num_insns = 0;
     max_insns = tb->cflags & CF_COUNT_MASK;
     if (max_insns == 0) {
@@ -11484,10 +11479,9 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
      * (3) if we leave the TB unexpectedly (eg a data abort on a load)
      * then the CPUARMState will be wrong and we need to reset it.
      * This is handled in the same way as restoration of the
-     * PC in these situations: we will be called again with search_pc=1
+     * PC in these situations; we save the value of the condexec bits
-     * and generate a mapping of the condexec bits for each PC in
+     * for each PC via tcg_gen_insn_start(), and restore_state_to_opc()
-     * gen_opc_condexec_bits[]. restore_state_to_opc() then uses
+     * then uses this to restore them after an exception.
-     * this to restore the condexec bits.
      *
      * Note that there are no instructions which can read the condexec
      * bits, and none which can write non-static values to them, so
@@ -11535,18 +11529,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
                 }
             }
         }
-        if (search_pc) {
+
-            j = tcg_op_buf_count(tcg_ctx);
-            if (lj < j) {
-                lj++;
-                while (lj < j)
-                    tcg_ctx->gen_opc_instr_start[lj++] = 0;
-            }
-            tcg_ctx->gen_opc_pc[lj] = dc->pc;
-            tcg_ctx->gen_opc_condexec_bits[lj] = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1);
-            tcg_ctx->gen_opc_instr_start[lj] = 1;
-            //tcg_ctx->gen_opc_icount[lj] = num_insns;
-        }
         tcg_gen_insn_start(tcg_ctx, dc->pc,
                            (dc->condexec_cond << 4) | (dc->condexec_mask >> 1));
         num_insns++;
@@ -11736,29 +11719,12 @@ tb_end:
 done_generating:
     gen_tb_end(tcg_ctx, tb, num_insns);
 
-    if (search_pc) {
-        j = tcg_op_buf_count(tcg_ctx);
-        lj++;
-        while (lj <= j)
-            tcg_ctx->gen_opc_instr_start[lj++] = 0;
-    } else {
     tb->size = dc->pc - pc_start;
-        //tb->icount = num_insns;
+    tb->icount = num_insns;
-    }
 
     env->uc->block_full = block_full;
 }
 
-void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
-{
-    gen_intermediate_code_internal(arm_env_get_cpu(env), tb, false);
-}
-
-void gen_intermediate_code_pc(CPUARMState *env, TranslationBlock *tb)
-{
-    gen_intermediate_code_internal(arm_env_get_cpu(env), tb, true);
-}
-
 #if 0
 static const char *cpu_mode_names[16] = {
   "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",

qemu/target-arm/translate.h

@@ -115,18 +115,14 @@ static inline int default_exception_el(DisasContext *s)
 
 #ifdef TARGET_AARCH64
 void a64_translate_init(struct uc_struct *uc);
-void gen_intermediate_code_internal_a64(ARMCPU *cpu,
+void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb);
-                                        TranslationBlock *tb,
-                                        bool search_pc);
 void gen_a64_set_pc_im(DisasContext *s, uint64_t val);
 #else
 static inline void a64_translate_init(struct uc_struct *uc)
 {
 }
 
-static inline void gen_intermediate_code_internal_a64(ARMCPU *cpu,
+static inline void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
-                                                      TranslationBlock *tb,
-                                                      bool search_pc)
 {
 }
 

qemu/target-i386/translate.c

@@ -8537,20 +8537,15 @@ void optimize_flags_init(struct uc_struct *uc)
 }
 
 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
-   basic block 'tb'. If search_pc is TRUE, also generate PC
+   basic block 'tb'.  */
-   information for each intermediate instruction. */
+void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
-static inline void gen_intermediate_code_internal(uint8_t *gen_opc_cc_op,
-                                                  X86CPU *cpu,
-                                                  TranslationBlock *tb,
-                                                  bool search_pc)
 {
+    X86CPU *cpu = x86_env_get_cpu(env);
     CPUState *cs = CPU(cpu);
-    CPUX86State *env = &cpu->env;
     TCGContext *tcg_ctx = env->uc->tcg_ctx;
     DisasContext dc1, *dc = &dc1;
     target_ulong pc_ptr;
     CPUBreakpoint *bp;
-    int j, lj;
     uint64_t flags;
     target_ulong pc_start;
     target_ulong cs_base;
@@ -8663,7 +8658,6 @@ static inline void gen_intermediate_code_internal(uint8_t *gen_opc_cc_op,
     }
 
     dc->is_jmp = DISAS_NEXT;
-    lj = -1;
     max_insns = tb->cflags & CF_COUNT_MASK;
     if (max_insns == 0) {
         max_insns = CF_COUNT_MASK;
@@ -8694,18 +8688,6 @@ static inline void gen_intermediate_code_internal(uint8_t *gen_opc_cc_op,
                 }
             }
         }
-        if (search_pc) {
-            j = tcg_op_buf_count(tcg_ctx);
-            if (lj < j) {
-                lj++;
-                while (lj < j)
-                    tcg_ctx->gen_opc_instr_start[lj++] = 0;
-            }
-            tcg_ctx->gen_opc_pc[lj] = pc_ptr;
-            gen_opc_cc_op[lj] = dc->cc_op;
-            tcg_ctx->gen_opc_instr_start[lj] = 1;
-            // tcg_ctx->gen_opc_icount[lj] = num_insns;
-        }
         tcg_gen_insn_start(tcg_ctx, pc_start, dc->cc_op);
         num_insns++;
 
@@ -8760,35 +8742,12 @@ static inline void gen_intermediate_code_internal(uint8_t *gen_opc_cc_op,
 done_generating:
     gen_tb_end(tcg_ctx, tb, num_insns);
 
-    /* we don't forget to fill the last values */
-    if (search_pc) {
-        j = tcg_op_buf_count(tcg_ctx);
-        lj++;
-        while (lj <= j)
-            tcg_ctx->gen_opc_instr_start[lj++] = 0;
-    }
-
-    if (!search_pc) {
     tb->size = pc_ptr - pc_start;
-    }
+    tb->icount = num_insns;
 
     env->uc->block_full = block_full;
 }
 
-void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
-{
-    TCGContext *tcg_ctx = env->uc->tcg_ctx;
-    gen_intermediate_code_internal(tcg_ctx->gen_opc_cc_op,
-            x86_env_get_cpu(env), tb, false);
-}
-
-void gen_intermediate_code_pc(CPUX86State *env, TranslationBlock *tb)
-{
-    TCGContext *tcg_ctx = env->uc->tcg_ctx;
-    gen_intermediate_code_internal(tcg_ctx->gen_opc_cc_op,
-            x86_env_get_cpu(env), tb, true);
-}
-
 void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb,
                           target_ulong *data)
 {

qemu/target-m68k/translate.c

@@ -3054,15 +3054,12 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
 }
 
 /* generate intermediate code for basic block 'tb'.  */
-static inline void
+void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
-gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
-                               bool search_pc)
 {
+    M68kCPU *cpu = m68k_env_get_cpu(env);
     CPUState *cs = CPU(cpu);
-    CPUM68KState *env = &cpu->env;
     DisasContext dc1, *dc = &dc1;
     CPUBreakpoint *bp;
-    int j, lj;
     target_ulong pc_start;
     int pc_offset;
     int num_insns;
@@ -3084,7 +3081,6 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
     dc->fpcr = env->fpcr;
     dc->user = (env->sr & SR_S) == 0;
     dc->done_mac = 0;
-    lj = -1;
     num_insns = 0;
     max_insns = tb->cflags & CF_COUNT_MASK;
     if (max_insns == 0) {
@@ -3127,20 +3123,10 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
             if (dc->is_jmp)
                 break;
         }
-        if (search_pc) {
-            j = tcg_op_buf_count(tcg_ctx);
-            if (lj < j) {
-                lj++;
-                while (lj < j)
-                    tcg_ctx->gen_opc_instr_start[lj++] = 0;
-            }
-            tcg_ctx->gen_opc_pc[lj] = dc->pc;
-            tcg_ctx->gen_opc_instr_start[lj] = 1;
-            //tcg_ctx.gen_opc_icount[lj] = num_insns;
-        }
         tcg_gen_insn_start(tcg_ctx, dc->pc);
         num_insns++;
 
+        // UNICORN: Commented out
         //if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
         //    gen_io_start();
         //}
@@ -3156,8 +3142,10 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
     if (tcg_op_buf_full(tcg_ctx) || num_insns >= max_insns)
         block_full = true;
 
-    //if (tb->cflags & CF_LAST_IO)
+    // UNICORN: Commented out
+    //if (tb->cflags & CF_LAST_IO) {
     //    gen_io_end();
+    //}
     if (unlikely(cs->singlestep_enabled)) {
         /* Make sure the pc is updated, and raise a debug exception.  */
         if (!dc->is_jmp) {
@@ -3187,32 +3175,12 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
 done_generating:
     gen_tb_end(tcg_ctx, tb, num_insns);
 
-    if (search_pc) {
-        j = tcg_op_buf_count(tcg_ctx);
-        lj++;
-        while (lj <= j)
-            tcg_ctx->gen_opc_instr_start[lj++] = 0;
-    } else {
     tb->size = dc->pc - pc_start;
-        //tb->icount = num_insns;
+    tb->icount = num_insns;
-    }
-
-    //optimize_flags();
-    //expand_target_qops();
 
     env->uc->block_full = block_full;
 }
 
-void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
-{
-    gen_intermediate_code_internal(m68k_env_get_cpu(env), tb, false);
-}
-
-void gen_intermediate_code_pc(CPUM68KState *env, TranslationBlock *tb)
-{
-    gen_intermediate_code_internal(m68k_env_get_cpu(env), tb, true);
-}
-
 void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
                           target_ulong *data)
 {

qemu/target-mips/translate.c

@@ -19694,17 +19694,14 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
     }
 }
 
-static inline void
+void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
-gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
-                               bool search_pc)
 {
+    MIPSCPU *cpu = mips_env_get_cpu(env);
     CPUState *cs = CPU(cpu);
-    CPUMIPSState *env = &cpu->env;
     DisasContext ctx;
     target_ulong pc_start;
     target_ulong next_page_start;
     CPUBreakpoint *bp;
-    int j, lj = -1;
     int num_insns;
     int max_insns;
     int insn_bytes;
@@ -19713,9 +19710,6 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
     int save_opparam_idx = -1;
     bool block_full = false;
 
-    if (search_pc)
-        qemu_log("search pc %d\n", search_pc);
-
     pc_start = tb->pc;
     next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
     ctx.uc = env->uc;
@@ -19794,22 +19788,10 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
             }
         }
 
-        if (search_pc) {
-            j = tcg_op_buf_count(tcg_ctx);
-            if (lj < j) {
-                lj++;
-                while (lj < j)
-                    tcg_ctx->gen_opc_instr_start[lj++] = 0;
-            }
-            tcg_ctx->gen_opc_pc[lj] = ctx.pc;
-            tcg_ctx->gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK;
-            tcg_ctx->gen_opc_btarget[lj] = ctx.btarget;
-            tcg_ctx->gen_opc_instr_start[lj] = 1;
-            tcg_ctx->gen_opc_icount[lj] = num_insns;
-        }
         tcg_gen_insn_start(tcg_ctx, ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btarget);
         num_insns++;
 
+        // Unicorn: Commented out
         //if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
         //    gen_io_start();
         //}
@@ -19931,29 +19913,12 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
 done_generating:
     gen_tb_end(tcg_ctx, tb, num_insns);
 
-    if (search_pc) {
-        j = tcg_op_buf_count(tcg_ctx);
-        lj++;
-        while (lj <= j)
-            tcg_ctx->gen_opc_instr_start[lj++] = 0;
-    } else {
     tb->size = ctx.pc - pc_start;
     tb->icount = num_insns;
-    }
 
     env->uc->block_full = block_full;
 }
 
-void gen_intermediate_code (CPUMIPSState *env, struct TranslationBlock *tb)
-{
-    gen_intermediate_code_internal(mips_env_get_cpu(env), tb, false);
-}
-
-void gen_intermediate_code_pc (CPUMIPSState *env, struct TranslationBlock *tb)
-{
-    gen_intermediate_code_internal(mips_env_get_cpu(env), tb, true);
-}
-
 #if 0
 static void fpu_dump_state(CPUMIPSState *env, FILE *f, fprintf_function fpu_fprintf,
                            int flags)

qemu/target-sparc/translate.c

@@ -5357,16 +5357,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
     }
 }
 
-static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
+void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
-                                                  TranslationBlock *tb,
-                                                  bool spc)
 {
+    SPARCCPU *cpu = sparc_env_get_cpu(env);
     CPUState *cs = CPU(cpu);
-    CPUSPARCState *env = &cpu->env;
     target_ulong pc_start, last_pc;
     DisasContext dc1, *dc = &dc1;
     CPUBreakpoint *bp;
-    int j, lj = -1;
     int num_insns = 0;
     int max_insns;
     unsigned int insn;
@@ -5387,7 +5384,6 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
     dc->address_mask_32bit = tb_am_enabled(tb->flags);
     dc->singlestep = (cs->singlestep_enabled); // || singlestep);
 
-
     // early check to see if the address of this block is the until address
     if (pc_start == env->uc->addr_end) {
         gen_tb_start(tcg_ctx);
@@ -5435,23 +5431,6 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
                 }
             }
         }
-        if (spc) {
-            qemu_log("Search PC...\n");
-            j = tcg_op_buf_count(tcg_ctx);
-            if (lj < j) {
-                lj++;
-                while (lj < j)
-                    tcg_ctx->gen_opc_instr_start[lj++] = 0;
-                tcg_ctx->gen_opc_pc[lj] = dc->pc;
-                tcg_ctx->gen_opc_npc[lj] = dc->npc;
-                if (dc->npc & JUMP_PC) {
-                    assert(dc->jump_pc[1] == dc->pc + 4);
-                    tcg_ctx->gen_opc_npc[lj] = dc->jump_pc[0] | JUMP_PC;
-                }
-                tcg_ctx->gen_opc_instr_start[lj] = 1;
-                tcg_ctx->gen_opc_icount[lj] = num_insns;
-            }
-        }
         if (dc->npc & JUMP_PC) {
             assert(dc->jump_pc[1] == dc->pc + 4);
             tcg_gen_insn_start(tcg_ctx, dc->pc, dc->jump_pc[0] | JUMP_PC);
@@ -5520,32 +5499,12 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
 done_generating:
     gen_tb_end(tcg_ctx, tb, num_insns);
 
-    if (spc) {
-        j = tcg_op_buf_count(tcg_ctx);
-        lj++;
-        while (lj <= j)
-            tcg_ctx->gen_opc_instr_start[lj++] = 0;
-#if 0
-        log_page_dump();
-#endif
-    } else {
     tb->size = last_pc + 4 - pc_start;
     tb->icount = num_insns;
-    }
 
     env->uc->block_full = block_full;
 }
 
-void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
-{
-    gen_intermediate_code_internal(sparc_env_get_cpu(env), tb, false);
-}
-
-void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
-{
-    gen_intermediate_code_internal(sparc_env_get_cpu(env), tb, true);
-}
-
 void gen_intermediate_code_init(CPUSPARCState *env)
 {
     TCGContext *tcg_ctx = env->uc->tcg_ctx;

qemu/tcg/tcg.h

@@ -723,7 +723,6 @@ struct TCGContext {
     TCGv_i32 cpu_cc_op;
     void *cpu_regs[16]; // 16 GRP for X86-64
     int x86_64_hregs;   // qemu/target-i386/translate.c
-    uint8_t gen_opc_cc_op[OPC_BUF_SIZE];    // qemu/target-i386/translate.c
 
     /* qemu/target-i386/translate.c: global TCGv vars */
     void *cpu_A0;
@@ -770,7 +769,6 @@ struct TCGContext {
     void *store_dummy;
 
     /* qemu/target-arm/translate.c */
-    uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
     TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
     /* We reuse the same 64-bit temporaries for efficiency.  */
     TCGv_i32 cpu_R[16];
@@ -796,9 +794,6 @@ struct TCGContext {
     TCGv_i64 fpu_f64[32];
     TCGv_i64 msa_wr_d[64];
 
-    uint32_t gen_opc_hflags[OPC_BUF_SIZE];
-    target_ulong gen_opc_btarget[OPC_BUF_SIZE];
-
     /* qemu/target-sparc/translate.c */
     /* global register indexes */
     TCGv_ptr cpu_regwptr;
@@ -808,8 +803,6 @@ struct TCGContext {
     /* Floating point registers */
     TCGv_i64 cpu_fpr[32];   // TARGET_DPREGS = 32 for Sparc64, 16 for Sparc
 
-    target_ulong gen_opc_npc[OPC_BUF_SIZE];
-
     // void *cpu_cc_src, *cpu_cc_src2, *cpu_cc_dst;
     void *cpu_fsr, *sparc_cpu_pc, *cpu_npc, *cpu_gregs[8];
     void *cpu_y;

qemu/x86_64.h

@@ -147,7 +147,6 @@
 #define arm_free_cc arm_free_cc_x86_64
 #define arm_generate_debug_exceptions arm_generate_debug_exceptions_x86_64
 #define gen_intermediate_code gen_intermediate_code_x86_64
-#define gen_intermediate_code_pc gen_intermediate_code_pc_x86_64
 #define arm_gen_test_cc arm_gen_test_cc_x86_64
 #define arm_gt_ptimer_cb arm_gt_ptimer_cb_x86_64
 #define arm_gt_vtimer_cb arm_gt_vtimer_cb_x86_64
@@ -1141,8 +1140,8 @@
 #define gen_helper_wfi gen_helper_wfi_x86_64
 #define gen_helper_yield gen_helper_yield_x86_64
 #define gen_hvc gen_hvc_x86_64
-#define gen_intermediate_code_internal gen_intermediate_code_internal_x86_64
+#define gen_intermediate_code gen_intermediate_code_x86_64
-#define gen_intermediate_code_internal_a64 gen_intermediate_code_internal_a64_x86_64
+#define gen_intermediate_code_a64 gen_intermediate_code_a64_x86_64
 #define gen_iwmmxt_address gen_iwmmxt_address_x86_64
 #define gen_iwmmxt_shift gen_iwmmxt_shift_x86_64
 #define gen_jmp gen_jmp_x86_64