mirror of
https://github.com/yuzu-emu/unicorn.git
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target/riscv: Split RVC32 and RVC64 insns into separate files
This eliminates all functions in insn_trans/trans_rvc.inc.c, so the entire file can be removed. Backports commit 0e68e240a9bd3b44a91cd6012f0e2bf2a43b9fe2 from qemu
This commit is contained in:
Richard Henderson
Lioncash
parent
a968769d26
commit
a62b4e5def
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@ -6,16 +6,19 @@ DECODETREE = $(SRC_PATH)/scripts/decodetree.py
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decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
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decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
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decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
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decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode
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decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
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target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
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$(call quiet-command, \
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$(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \
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$(decode32-y), "GEN", $(TARGET_DIR)$@)
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target/riscv/decode_insn16.inc.c: \
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$(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
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target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE)
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$(call quiet-command, \
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$(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \
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--insnwidth 16 $<, "GEN", $(TARGET_DIR)$@)
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--insnwidth 16 $(decode16-y), "GEN", $(TARGET_DIR)$@)
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target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
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target/riscv/decode_insn16.inc.c
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28
qemu/target/riscv/insn16-32.decode
Normal file
28
qemu/target/riscv/insn16-32.decode
Normal file
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@ -0,0 +1,28 @@
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#
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# RISC-V translation routines for the RVXI Base Integer Instruction Set.
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#
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# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
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# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms and conditions of the GNU General Public License,
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# version 2 or later, as published by the Free Software Foundation.
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#
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# This program is distributed in the hope it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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#
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# You should have received a copy of the GNU General Public License along with
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# this program. If not, see <http://www.gnu.org/licenses/>.
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# *** RV32C Standard Extension (Quadrant 0) ***
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flw 011 ... ... .. ... 00 @cl_w
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fsw 111 ... ... .. ... 00 @cs_w
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# *** RV32C Standard Extension (Quadrant 1) ***
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jal 001 ........... 01 @cj rd=1 # C.JAL
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# *** RV32C Standard Extension (Quadrant 2) ***
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flw 011 . ..... ..... 10 @c_lwsp
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fsw 111 . ..... ..... 10 @c_swsp
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30
qemu/target/riscv/insn16-64.decode
Normal file
30
qemu/target/riscv/insn16-64.decode
Normal file
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@ -0,0 +1,30 @@
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#
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# RISC-V translation routines for the RVXI Base Integer Instruction Set.
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#
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# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
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# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms and conditions of the GNU General Public License,
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# version 2 or later, as published by the Free Software Foundation.
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#
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# This program is distributed in the hope it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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#
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# You should have received a copy of the GNU General Public License along with
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# this program. If not, see <http://www.gnu.org/licenses/>.
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# *** RV64C Standard Extension (Quadrant 0) ***
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ld 011 ... ... .. ... 00 @cl_d
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sd 111 ... ... .. ... 00 @cs_d
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# *** RV64C Standard Extension (Quadrant 1) ***
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addiw 001 . ..... ..... 01 @ci
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subw 100 1 11 ... 00 ... 01 @cs_2
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addw 100 1 11 ... 01 ... 01 @cs_2
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# *** RV64C Standard Extension (Quadrant 2) ***
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ld 011 . ..... ..... 10 @c_ldsp
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sd 111 . ..... ..... 10 @c_sdsp
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@ -50,30 +50,11 @@
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&u imm rd !extern
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&shift shamt rs1 rd !extern
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# Argument sets:
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&cl rs1 rd
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&cl_dw uimm rs1 rd
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&ciw nzuimm rd
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&cs rs1 rs2
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&cs_dw uimm rs1 rs2
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&cb imm rs1
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&cr rd rs2
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&c_shift shamt rd
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&c_ld uimm rd
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&c_sd uimm rs2
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&caddi16sp_lui imm_lui imm_addi16sp rd
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&cflwsp_ldsp uimm_flwsp uimm_ldsp rd
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&cfswsp_sdsp uimm_fswsp uimm_sdsp rs2
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# Formats 16:
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@cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
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@ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd
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@cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
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@cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
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@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3
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@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3
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@cs_2 ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 rd=%rs1_3
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@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
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@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
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@ -91,10 +72,6 @@
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@c_addi4spn ... . ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
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@c_addi16sp ... . ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2
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@c_flwsp_ldsp ... . ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
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uimm_ldsp=%uimm_6bit_ld %rd
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@c_fswsp_sdsp ... . ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
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uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
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@c_shift ... . .. ... ..... .. \
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&shift rd=%rs1_3 rs1=%rs1_3 shamt=%shimm_6bit
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@ -104,7 +81,7 @@
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@c_andi ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
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# *** RV64C Standard Extension (Quadrant 0) ***
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# *** RV32/64C Standard Extension (Quadrant 0) ***
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{
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# Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
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illegal 000 000 000 00 --- 00
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@ -112,14 +89,11 @@
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}
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fld 001 ... ... .. ... 00 @cl_d
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lw 010 ... ... .. ... 00 @cl_w
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c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually
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fsd 101 ... ... .. ... 00 @cs_d
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sw 110 ... ... .. ... 00 @cs_w
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c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually
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# *** RV64C Standard Extension (Quadrant 1) ***
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# *** RV32/64C Standard Extension (Quadrant 1) ***
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addi 000 . ..... ..... 01 @ci
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c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm manually
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addi 010 . ..... ..... 01 @c_li
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{
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addi 011 . 00010 ..... 01 @c_addi16sp
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@ -132,17 +106,14 @@ sub 100 0 11 ... 00 ... 01 @cs_2
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xor 100 0 11 ... 01 ... 01 @cs_2
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or 100 0 11 ... 10 ... 01 @cs_2
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and 100 0 11 ... 11 ... 01 @cs_2
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c_subw 100 1 11 ... 00 ... 01 @cs_2
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c_addw 100 1 11 ... 01 ... 01 @cs_2
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jal 101 ........... 01 @cj rd=0 # C.J
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beq 110 ... ... ..... 01 @cb_z
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bne 111 ... ... ..... 01 @cb_z
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# *** RV64C Standard Extension (Quadrant 2) ***
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# *** RV32/64C Standard Extension (Quadrant 2) ***
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slli 000 . ..... ..... 10 @c_shift2
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fld 001 . ..... ..... 10 @c_ldsp
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lw 010 . ..... ..... 10 @c_lwsp
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c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
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{
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jalr 100 0 ..... 00000 10 @c_jalr rd=0 # C.JR
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addi 100 0 ..... ..... 10 @c_mv
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@ -154,4 +125,3 @@ c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
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}
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fsd 101 ...... ..... 10 @c_sdsp
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sw 110 . ..... ..... 10 @c_swsp
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c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32
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@ -1,115 +0,0 @@
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/*
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* RISC-V translation routines for the RVC Compressed Instruction Set.
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
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* Bastian Koppelmann, kbastian@mail.uni-paderborn.de
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
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{
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#ifdef TARGET_RISCV32
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/* C.FLW ( RV32FC-only ) */
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REQUIRE_FPU;
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REQUIRE_EXT(ctx, RVF);
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arg_i arg;
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decode_insn16_extract_cl_w(ctx, &arg, ctx->opcode);
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return trans_flw(ctx, &arg);
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#else
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/* C.LD ( RV64C/RV128C-only ) */
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arg_i arg;
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decode_insn16_extract_cl_d(ctx, &arg, ctx->opcode);
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return trans_ld(ctx, &arg);
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#endif
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}
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static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
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{
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#ifdef TARGET_RISCV32
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/* C.FSW ( RV32FC-only ) */
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REQUIRE_FPU;
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REQUIRE_EXT(ctx, RVF);
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arg_s arg;
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decode_insn16_extract_cs_w(ctx, &arg, ctx->opcode);
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return trans_fsw(ctx, &arg);
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#else
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/* C.SD ( RV64C/RV128C-only ) */
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arg_s arg;
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decode_insn16_extract_cs_d(ctx, &arg, ctx->opcode);
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return trans_sd(ctx, &arg);
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#endif
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}
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static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
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{
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#ifdef TARGET_RISCV32
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/* C.JAL */
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arg_j tmp;
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decode_insn16_extract_cj(ctx, &tmp, ctx->opcode);
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arg_jal arg = { .rd = 1, .imm = tmp.imm };
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return trans_jal(ctx, &arg);
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#else
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/* C.ADDIW */
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arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
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return trans_addiw(ctx, &arg);
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#endif
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}
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static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
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{
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#ifdef TARGET_RISCV64
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return trans_subw(ctx, a);
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#else
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return false;
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#endif
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}
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static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
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{
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#ifdef TARGET_RISCV64
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return trans_addw(ctx, a);
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#else
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return false;
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#endif
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}
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static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
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{
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#ifdef TARGET_RISCV32
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/* C.FLWSP */
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arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp };
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return trans_flw(ctx, &arg_flw);
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#else
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/* C.LDSP */
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arg_ld arg_ld = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_ldsp };
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return trans_ld(ctx, &arg_ld);
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#endif
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return false;
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}
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static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
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{
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#ifdef TARGET_RISCV32
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/* C.FSWSP */
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arg_fsw a_fsw = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_fswsp };
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return trans_fsw(ctx, &a_fsw);
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#else
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/* C.SDSP */
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arg_sd a_sd = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_sdsp };
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return trans_sd(ctx, &a_sd);
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#endif
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}
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@ -735,7 +735,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
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#endif
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#include "decode_insn16.inc.c"
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#include "insn_trans/trans_rvc.inc.c"
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#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
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# pragma GCC diagnostic pop
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