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target/arm: Use vector infrastructure for aa64 dup/movi

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Backports commit 861a1ded24917843b9a5a99ea0a6b37c2c9a1930 from qemu
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Richard Henderson 2018-03-06 15:46:09 -05:00 committed by Lioncash
parent 84f848d876
commit a63be5a7aa
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 33 additions and 49 deletions
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58
qemu/target/arm/translate-a64.c
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@ -5997,10 +5997,7 @@ static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn,
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
int size = ctz32(imm5);
int esize = 8 << size;
int elements = (is_q ? 128 : 64) / esize;
int index, i;
TCGv_i64 tmp;
int index = imm5 >> (size + 1);
if (size > 3 || (size == 3 && !is_q)) {
unallocated_encoding(s);
@ -6011,20 +6008,9 @@ static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn,
return;
}
index = imm5 >> (size + 1);
tmp = tcg_temp_new_i64(tcg_ctx);
read_vec_element(s, tmp, rn, index, size);
for (i = 0; i < elements; i++) {
write_vec_element(s, tmp, rd, i, size);
}
if (!is_q) {
clear_vec_high(s, rd);
}
tcg_temp_free_i64(tcg_ctx, tmp);
tcg_gen_gvec_dup_mem(tcg_ctx, size, vec_full_reg_offset(s, rd),
vec_reg_offset(s, rn, index, size),
is_q ? 16 : 8, vec_full_reg_size(s));
}
/* DUP (element, scalar)
@ -6073,10 +6059,9 @@ static void handle_simd_dupes(DisasContext *s, int rd, int rn,
static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn,
int imm5)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
int size = ctz32(imm5);
int esize = 8 << size;
int elements = (is_q ? 128 : 64)/esize;
int i = 0;
uint32_t dofs, oprsz, maxsz;
if (size > 3 || ((size == 3) && !is_q)) {
unallocated_encoding(s);
@ -6087,12 +6072,11 @@ static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn,
return;
}
for (i = 0; i < elements; i++) {
write_vec_element(s, cpu_reg(s, rn), rd, i, size);
}
if (!is_q) {
clear_vec_high(s, rd);
}
dofs = vec_full_reg_offset(s, rd);
oprsz = is_q ? 16 : 8;
maxsz = vec_full_reg_size(s);
tcg_gen_gvec_dup_i64(tcg_ctx, size, dofs, oprsz, maxsz, cpu_reg(s, rn));
}
/* INS (Element)
@ -6286,7 +6270,6 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
bool is_neg = extract32(insn, 29, 1);
bool is_q = extract32(insn, 30, 1);
uint64_t imm = 0;
TCGv_i64 tcg_rd, tcg_imm;
int i;
if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
@ -6368,16 +6351,20 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
imm = ~imm;
}
tcg_imm = tcg_const_i64(tcg_ctx, imm);
tcg_rd = new_tmp_a64(s);
if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
/* MOVI or MVNI, with MVNI negation handled above. */
tcg_gen_gvec_dup64i(tcg_ctx, vec_full_reg_offset(s, rd), is_q ? 16 : 8,
vec_full_reg_size(s), imm);
} else {
TCGv_i64 tcg_imm = tcg_const_i64(tcg_ctx, imm);
TCGv_i64 tcg_rd = new_tmp_a64(s);
for (i = 0; i < 2; i++) {
int foffs = i ? fp_reg_hi_offset(s, rd) : fp_reg_offset(s, rd, MO_64);
int foffs = vec_reg_offset(s, rd, i, MO_64);
if (i == 1 && !is_q) {
/* non-quad ops clear high half of vector */
tcg_gen_movi_i64(tcg_ctx, tcg_rd, 0);
} else if ((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9) {
} else {
tcg_gen_ld_i64(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, foffs);
if (is_neg) {
/* AND (BIC) */
@ -6386,15 +6373,12 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
/* ORR */
tcg_gen_or_i64(tcg_ctx, tcg_rd, tcg_rd, tcg_imm);
}
} else {
/* MOVI */
tcg_gen_mov_i64(tcg_ctx, tcg_rd, tcg_imm);
}
tcg_gen_st_i64(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, foffs);
}
tcg_temp_free_i64(tcg_ctx, tcg_imm);
}
}
/* AdvSIMD scalar copy
* 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0