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target/riscv: Allow setting a two-stage lookup in the virt status

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Backports 5a894dd7709f3b6a9f3e861dec71f78098bb3373
This commit is contained in:
Alistair Francis 2021-03-08 12:49:08 -05:00 committed by Lioncash
parent 9792907bcf
commit a8bce9af7a
6 changed files with 27 additions and 1 deletions
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2
qemu/header_gen.py
View file

@ -7320,9 +7320,11 @@ riscv_symbols = (
'riscv_cpu_set_force_hs_excep',
'riscv_cpu_set_mode',
'riscv_cpu_set_rdtime_fn',
'riscv_cpu_set_two_stage_lookup',
'riscv_cpu_set_virt_enabled',
'riscv_cpu_swap_hypervisor_regs',
'riscv_cpu_tlb_fill',
'riscv_cpu_two_stage_lookup',
'riscv_cpu_unassigned_access',
'riscv_cpu_update_mip',
'riscv_cpu_virt_enabled',

2
qemu/riscv32.h
View file

@ -4756,9 +4756,11 @@
#define riscv_cpu_set_force_hs_excep riscv_cpu_set_force_hs_excep_riscv32
#define riscv_cpu_set_mode riscv_cpu_set_mode_riscv32
#define riscv_cpu_set_rdtime_fn riscv_cpu_set_rdtime_fn_riscv32
#define riscv_cpu_set_two_stage_lookup riscv_cpu_set_two_stage_lookup_riscv32
#define riscv_cpu_set_virt_enabled riscv_cpu_set_virt_enabled_riscv32
#define riscv_cpu_swap_hypervisor_regs riscv_cpu_swap_hypervisor_regs_riscv32
#define riscv_cpu_tlb_fill riscv_cpu_tlb_fill_riscv32
#define riscv_cpu_two_stage_lookup riscv_cpu_two_stage_lookup_riscv32
#define riscv_cpu_unassigned_access riscv_cpu_unassigned_access_riscv32
#define riscv_cpu_update_mip riscv_cpu_update_mip_riscv32
#define riscv_cpu_virt_enabled riscv_cpu_virt_enabled_riscv32

2
qemu/riscv64.h
View file

@ -4756,9 +4756,11 @@
#define riscv_cpu_set_force_hs_excep riscv_cpu_set_force_hs_excep_riscv64
#define riscv_cpu_set_mode riscv_cpu_set_mode_riscv64
#define riscv_cpu_set_rdtime_fn riscv_cpu_set_rdtime_fn_riscv64
#define riscv_cpu_set_two_stage_lookup riscv_cpu_set_two_stage_lookup_riscv64
#define riscv_cpu_set_virt_enabled riscv_cpu_set_virt_enabled_riscv64
#define riscv_cpu_swap_hypervisor_regs riscv_cpu_swap_hypervisor_regs_riscv64
#define riscv_cpu_tlb_fill riscv_cpu_tlb_fill_riscv64
#define riscv_cpu_two_stage_lookup riscv_cpu_two_stage_lookup_riscv64
#define riscv_cpu_unassigned_access riscv_cpu_unassigned_access_riscv64
#define riscv_cpu_update_mip riscv_cpu_update_mip_riscv64
#define riscv_cpu_virt_enabled riscv_cpu_virt_enabled_riscv64

2
qemu/target/riscv/cpu.h
View file

@ -324,6 +324,8 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
bool riscv_cpu_two_stage_lookup(CPURISCVState *env);
void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,

2
qemu/target/riscv/cpu_bits.h
View file

@ -468,7 +468,7 @@
* page table fault.
*/
#define FORCE_HS_EXCEP 2
#define HS_TWO_STAGE 4
/* RV32 satp CSR field masks */
#define SATP32_MODE 0x80000000

18
qemu/target/riscv/cpu_helper.c
View file

@ -220,6 +220,24 @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable)
env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable);
}
bool riscv_cpu_two_stage_lookup(CPURISCVState *env)
{
if (!riscv_has_ext(env, RVH)) {
return false;
}
return get_field(env->virt, HS_TWO_STAGE);
}
void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable)
{
if (!riscv_has_ext(env, RVH)) {
return;
}
env->virt = set_field(env->virt, HS_TWO_STAGE, enable);
}
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
{
CPURISCVState *env = &cpu->env;