yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2024-12-23 05:25:31 +00:00
Code Issues Packages Projects Releases Wiki Activity

target-arm: Remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3

Browse source 
The regdefs for the ESR_EL2 and ESR_EL3 system registers should not
be marked as ARM_CP_ALIAS, because these are the master copies; the
DFSR regdef in vmsa_pmsa_cp_reginfo[] is marked as an alias.
Remove the ALIAS tags so that these registers are correctly migrated.

Backports commit 094a7d0b9d10812d06be2c5c19288cee4603c693 from qemu
This commit is contained in:
Peter Maydell 2018-02-22 11:40:13 -05:00 committed by Lioncash
parent f1b5b5cea9
commit a93e873441
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 4 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
qemu/target-arm/helper.c
View file

@ -3097,8 +3097,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
NULL, NULL, hcr_write },
{ "ELR_EL2", 0,4,0, 3,4,1, ARM_CP_STATE_AA64,
ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, elr_el[2]) },
{ "ESR_EL2", 0,5,2, 3,4,0, ARM_CP_STATE_AA64,
ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.esr_el[2]) },
{ "ESR_EL2", 0,5,2, 3,4,0, ARM_CP_STATE_AA64, 0,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.esr_el[2]) },
{ "FAR_EL2", 0,6,0, 3,4,0, ARM_CP_STATE_AA64,
0, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.far_el[2]) },
{ "SPSR_EL2", 0,4,0, 3,4,0, ARM_CP_STATE_AA64,
@ -3268,8 +3268,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
NULL, NULL, vmsa_tcr_el1_write, NULL, raw_write, vmsa_ttbcr_reset },
{ "ELR_EL3", 0,4,0, 3,6,1, ARM_CP_STATE_AA64,
ARM_CP_ALIAS, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, elr_el[3]) },
{ "ESR_EL3", 0,5,2, 3,6,0, ARM_CP_STATE_AA64,
ARM_CP_ALIAS, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.esr_el[3]) },
{ "ESR_EL3", 0,5,2, 3,6,0, ARM_CP_STATE_AA64, 0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.esr_el[3]) },
{ "FAR_EL3", 0,6,0, 3,6,0, ARM_CP_STATE_AA64,
0, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.far_el[3]) },
{ "SPSR_EL3", 0,4,0, 3,6,0, ARM_CP_STATE_AA64,