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cputlb: Byte swap memory transaction attribute

Browse source 
Notice new attribute, byte swap, and force the transaction through the
memory slow path.

Required by architectures that can invert endianness of memory
transaction, e.g. SPARC64 has the Invert Endian TTE bit.

Backports commit a26fc6f5152b47f1d7ed928f9c9d462d01ff1624 from qemu
This commit is contained in:
Tony Nguyen 2020-01-07 19:15:28 -05:00 committed by Lioncash
parent 103d6f51c8
commit a95927de1d
2 changed files with 14 additions and 0 deletions
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12
qemu/accel/tcg/cputlb.c
View file

@ -385,6 +385,10 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
*/
address |= TLB_RECHECK;
}
if (attrs.byte_swap) {
/* Force the access through the I/O slow path. */
address |= TLB_MMIO;
}
if (!memory_region_is_ram(section->mr) &&
!memory_region_is_romd(section->mr)) {
/* IO memory case */
@ -594,6 +598,10 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
uint64_t val;
MemTxResult r;
if (iotlbentry->attrs.byte_swap) {
op ^= MO_BSWAP;
}
section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
mr = section->mr;
mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
@ -627,6 +635,10 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
MemoryRegion *mr;
MemTxResult r;
if (iotlbentry->attrs.byte_swap) {
op ^= MO_BSWAP;
}
section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
mr = section->mr;
mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;

2
qemu/include/exec/memattrs.h
View file

@ -37,6 +37,8 @@ typedef struct MemTxAttrs {
unsigned int user:1;
/* Requester ID (for MSI for example) */
unsigned int requester_id:16;
/* Invert endianness for this page */
unsigned int byte_swap:1;
/*
* The following are target-specific page-table bits. These are not
* related to actual memory transactions at all. However, this structure