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target/riscv: Add a virtualised MMU Mode

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Add a new MMU mode that includes the current virt mode.

Backports c445593d30037d0c82241e8ec23eb845bca476e9
This commit is contained in:
Alistair Francis 2021-03-08 14:56:06 -05:00 committed by Lioncash
parent 757608b77c
commit a998c18ad8
3 changed files with 15 additions and 3 deletions
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12
qemu/target/riscv/cpu-param.h
View file

@ -18,6 +18,16 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
#endif
#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
#define NB_MMU_MODES 4
/*
* The current MMU Modes are:
* - U mode 0b000
* - S mode 0b001
* - M mode 0b011
* - U mode HLV/HLVX/HSV 0b100
* - S mode HLV/HLVX/HSV 0b101
* - M mode HLV/HLVX/HSV 0b111
*/
#define NB_MMU_MODES 8
#endif

4
qemu/target/riscv/cpu.h
View file

@ -365,7 +365,9 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
#define TB_FLAGS_MMU_MASK 3
#define TB_FLAGS_MMU_MASK 7
#define TB_FLAGS_PRIV_MMU_MASK 3
#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
typedef CPURISCVState CPUArchState;

2
qemu/target/riscv/cpu_helper.c
View file

@ -317,7 +317,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
* (riscv_cpu_do_interrupt) is correct */
MemTxResult res;
MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
int mode = mmu_idx;
int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
bool use_background = false;
/*