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target/arm: Implement M-profile "minimal RAS implementation"

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For v8.1M the architecture mandates that CPUs must provide at
least the "minimal RAS implementation" from the Reliability,
Availability and Serviceability extension. This consists of:
* an ESB instruction which is a NOP
-- since it is in the HINT space we need only add a comment
* an RFSR register which will RAZ/WI
* a RAZ/WI AIRCR.IESB bit
-- the code which handles writes to AIRCR does not allow setting
of RES0 bits, so we already treat this as RAZ/WI; add a comment
noting that this is deliberate
* minimal implementation of the RAS register block at 0xe0005000
-- this will be in a subsequent commit
* setting the ID_PFR0.RAS field to 0b0010
-- we will do this when we add the Cortex-M55 CPU model

Backports 46f4976f22a4549322307b34272e053d38653243
This commit is contained in:
Peter Maydell 2021-03-03 19:07:20 -05:00 committed by Lioncash
parent 543483444d
commit a9abb7c647
2 changed files with 18 additions and 0 deletions
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14
qemu/target/arm/cpu.h
View file

@ -1691,6 +1691,15 @@ FIELD(ID_MMFR4, LSM, 20, 4)
FIELD(ID_MMFR4, CCIDX, 24, 4) FIELD(ID_MMFR4, CCIDX, 24, 4)
FIELD(ID_MMFR4, EVT, 28, 4) FIELD(ID_MMFR4, EVT, 28, 4)
FIELD(ID_PFR0, STATE0, 0, 4)
FIELD(ID_PFR0, STATE1, 4, 4)
FIELD(ID_PFR0, STATE2, 8, 4)
FIELD(ID_PFR0, STATE3, 12, 4)
FIELD(ID_PFR0, CSV2, 16, 4)
FIELD(ID_PFR0, AMU, 20, 4)
FIELD(ID_PFR0, DIT, 24, 4)
FIELD(ID_PFR0, RAS, 28, 4)
FIELD(ID_PFR1, PROGMOD, 0, 4) FIELD(ID_PFR1, PROGMOD, 0, 4)
FIELD(ID_PFR1, SECURITY, 4, 4) FIELD(ID_PFR1, SECURITY, 4, 4)
FIELD(ID_PFR1, MPROGMOD, 8, 4) FIELD(ID_PFR1, MPROGMOD, 8, 4)
@ -3418,6 +3427,11 @@ static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
} }
static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
{
return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0;
}
static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
{ {
return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;

4
qemu/target/arm/t32.decode
View file

@ -307,6 +307,10 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
# SEV 1111 0011 1010 1111 1000 0000 0000 0100 # SEV 1111 0011 1010 1111 1000 0000 0000 0100
# SEVL 1111 0011 1010 1111 1000 0000 0000 0101 # SEVL 1111 0011 1010 1111 1000 0000 0000 0101
# For M-profile minimal-RAS ESB can be a NOP, which is the
# default behaviour since it is in the hint space.
# ESB 1111 0011 1010 1111 1000 0000 0001 0000
# The canonical nop ends in 0000 0000, but the whole rest # The canonical nop ends in 0000 0000, but the whole rest
# of the space is "reserved hint, behaves as nop". # of the space is "reserved hint, behaves as nop".
NOP 1111 0011 1010 1111 1000 0000 ---- ---- NOP 1111 0011 1010 1111 1000 0000 ---- ----