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target-sparc: implement UA2005 ASI_MMU (0x21)

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Backports commit 7dd8c0760ee197420273a7dfeab13bf54f6bbd8d from qemu
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Artyom Tarasenko 2018-03-01 22:25:37 -05:00 committed by Lioncash
parent aac6955197
commit aa24403d8a
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 31 additions and 0 deletions
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31
qemu/target-sparc/ldst_helper.c
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@ -1410,6 +1410,18 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
ret = env->scratch[i];
break;
}
case ASI_MMU: /* UA2005 Context ID registers */
switch ((addr >> 3) & 0x3) {
case 1:
ret = env->dmmu.mmu_primary_context;
break;
case 2:
ret = env->dmmu.mmu_secondary_context;
break;
default:
cpu_unassigned_access(cs, addr, true, false, 1, size);
}
break;
case ASI_DCACHE_DATA: /* D-cache data */
case ASI_DCACHE_TAG: /* D-cache tag access */
case ASI_ESTATE_ERROR_EN: /* E-cache error enable */
@ -1717,6 +1729,25 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
case ASI_INTR_RECEIVE: /* Interrupt data receive */
env->ivec_status = val & 0x20;
return;
case ASI_MMU: /* UA2005 Context ID registers */
{
switch ((addr >> 3) & 0x3) {
case 1:
env->dmmu.mmu_primary_context = val;
env->immu.mmu_primary_context = val;
tlb_flush_by_mmuidx(CPU(cpu), MMU_USER_IDX, MMU_KERNEL_IDX, -1);
break;
case 2:
env->dmmu.mmu_secondary_context = val;
env->immu.mmu_secondary_context = val;
tlb_flush_by_mmuidx(CPU(cpu), MMU_USER_SECONDARY_IDX,
MMU_KERNEL_SECONDARY_IDX, -1);
break;
default:
cpu_unassigned_access(cs, addr, true, false, 1, size);
}
}
return;
case ASI_QUEUE: /* UA2005 CPU mondo queue */
case ASI_DCACHE_DATA: /* D-cache data */
case ASI_DCACHE_TAG: /* D-cache tag access */