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target/arm: Implement VFP fp16 VLDR and VSTR

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Implement the fp16 versions of the VFP VLDR/VSTR (immediate).

Backports commit 274afbb121107b8aaeaa11b3e7904d5f8ae38a94
This commit is contained in:
Peter Maydell 2021-02-28 04:58:29 -05:00 committed by Lioncash
parent 5d98e14545
commit ac9ae5cbe7
2 changed files with 37 additions and 2 deletions
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36
qemu/target/arm/translate-vfp.inc.c
View file

@ -899,6 +899,42 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a)
return true; return true;
} }
static bool trans_VLDR_VSTR_hp(DisasContext *s, arg_VLDR_VSTR_sp *a)
{
uint32_t offset;
TCGv_i32 addr, tmp;
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (!dc_isar_feature(aa32_fp16_arith, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
/* imm8 field is offset/2 for fp16, unlike fp32 and fp64 */
offset = a->imm << 1;
if (!a->u) {
offset = -offset;
}
/* For thumb, use of PC is UNPREDICTABLE. */
addr = add_reg_for_lit(s, a->rn, offset);
tmp = tcg_temp_new_i32(tcg_ctx);
if (a->l) {
gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
neon_store_reg32(s, tmp, a->vd);
} else {
neon_load_reg32(s, tmp, a->vd);
gen_aa32_st16(s, tmp, addr, get_mem_index(s));
}
tcg_temp_free_i32(tcg_ctx, tmp);
tcg_temp_free_i32(tcg_ctx, addr);
return true;
}
static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a) static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;

3
qemu/target/arm/vfp.decode
View file

@ -79,8 +79,7 @@ VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 vn=%vn_sp
VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... vm=%vm_sp VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... vm=%vm_sp
VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... vm=%vm_dp VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... vm=%vm_dp
# Note that the half-precision variants of VLDR and VSTR are VLDR_VSTR_hp ---- 1101 u:1 .0 l:1 rn:4 .... 1001 imm:8 vd=%vd_sp
# not part of this decodetree at all because they have bits [9:8] == 0b01
VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp
VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp