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target-arm: Enable EL2 feature bit on A53 and A57

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Enable the ARM_FEATURE_EL2 bit on Cortex-A52 and
Cortex-A57, since this is all now sufficiently implemented
to work with the GICv3. We provide the usual CPU property
to disable it for backwards compatibility with the older
virt boards.

In this commit, we disable the EL2 feature on the
virt and ZynpMP boards, so there is no overall effect.
Another commit will expose a board-level property to
allow the user to enable EL2.

Backports commit c25bd18a04c8bd0f19556d719864b7b08528222d from qemu
This commit is contained in:
Peter Maydell 2018-03-01 23:36:39 -05:00 committed by Lioncash
parent a036c73de8
commit aca671b3b1
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GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 8 additions and 0 deletions
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4
qemu/target/arm/cpu.c
View file

@ -540,6 +540,10 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
cpu->id_aa64pfr0 &= ~0xf000; cpu->id_aa64pfr0 &= ~0xf000;
} }
if (!cpu->has_el2) {
unset_feature(env, ARM_FEATURE_EL2);
}
if (!cpu->has_pmu) { if (!cpu->has_pmu) {
cpu->has_pmu = false; cpu->has_pmu = false;
unset_feature(env, ARM_FEATURE_PMU); unset_feature(env, ARM_FEATURE_PMU);

2
qemu/target/arm/cpu.h
View file

@ -585,6 +585,8 @@ typedef struct ARMCPU {
bool start_powered_off; bool start_powered_off;
/* CPU currently in PSCI powered-off state */ /* CPU currently in PSCI powered-off state */
bool powered_off; bool powered_off;
/* CPU has virtualization extension */
bool has_el2;
/* CPU has security extension */ /* CPU has security extension */
bool has_el3; bool has_el3;
/* CPU has PMU (Performance Monitor Unit) */ /* CPU has PMU (Performance Monitor Unit) */

2
qemu/target/arm/cpu64.c
View file

@ -92,6 +92,7 @@ static void aarch64_a57_initfn(struct uc_struct *uc, Object *obj, void *opaque)
set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
set_feature(&cpu->env, ARM_FEATURE_CRC); set_feature(&cpu->env, ARM_FEATURE_CRC);
set_feature(&cpu->env, ARM_FEATURE_EL2);
set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_EL3);
set_feature(&cpu->env, ARM_FEATURE_PMU); set_feature(&cpu->env, ARM_FEATURE_PMU);
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
@ -148,6 +149,7 @@ static void aarch64_a53_initfn(struct uc_struct *uc, Object *obj, void *opaque)
set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
set_feature(&cpu->env, ARM_FEATURE_CRC); set_feature(&cpu->env, ARM_FEATURE_CRC);
set_feature(&cpu->env, ARM_FEATURE_EL2);
set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_EL3);
set_feature(&cpu->env, ARM_FEATURE_PMU); set_feature(&cpu->env, ARM_FEATURE_PMU);
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;