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target/arm: Fix aa64 ldp register writeback

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Backports commit 3e4d91b94ce400326fae0850578d9e9f30a71adb from qemu
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Richard Henderson 2018-02-08 08:28:43 -05:00 committed by Lioncash
parent 37cdcbf771
commit afb67fc002
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 16 additions and 11 deletions
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27
qemu/target-arm/translate-a64.c
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@ -1986,29 +1986,34 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
} else { } else {
do_fp_st(s, rt, tcg_addr, size); do_fp_st(s, rt, tcg_addr, size);
} }
} else { tcg_gen_addi_i64(tcg_ctx, tcg_addr, tcg_addr, 1 << size);
TCGv_i64 tcg_rt = cpu_reg(s, rt);
if (is_load) {
do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false);
} else {
do_gpr_st(s, tcg_rt, tcg_addr, size);
}
}
tcg_gen_addi_i64(tcg_ctx, tcg_addr, tcg_addr, 1ULL << size);
if (is_vector) {
if (is_load) { if (is_load) {
do_fp_ld(s, rt2, tcg_addr, size); do_fp_ld(s, rt2, tcg_addr, size);
} else { } else {
do_fp_st(s, rt2, tcg_addr, size); do_fp_st(s, rt2, tcg_addr, size);
} }
} else { } else {
TCGv_i64 tcg_rt = cpu_reg(s, rt);
TCGv_i64 tcg_rt2 = cpu_reg(s, rt2); TCGv_i64 tcg_rt2 = cpu_reg(s, rt2);
if (is_load) { if (is_load) {
TCGv_i64 tmp = tcg_temp_new_i64(tcg_ctx);
/* Do not modify tcg_rt before recognizing any exception
* from the second load.
*/
do_gpr_ld(s, tmp, tcg_addr, size, is_signed, false);
tcg_gen_addi_i64(tcg_ctx, tcg_addr, tcg_addr, 1 << size);
do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false); do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false);
tcg_gen_mov_i64(tcg_ctx, tcg_rt, tmp);
tcg_temp_free_i64(tcg_ctx, tmp);
} else { } else {
do_gpr_st(s, tcg_rt, tcg_addr, size);
tcg_gen_addi_i64(tcg_ctx, tcg_addr, tcg_addr, 1 << size);
do_gpr_st(s, tcg_rt2, tcg_addr, size); do_gpr_st(s, tcg_rt2, tcg_addr, size);
} }
} }
if (wback) { if (wback) {
if (postindex) { if (postindex) {