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target/arm: Use tcg_gen_gvec_dup_imm

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In a few cases, we're able to remove some manual replication.

Backports commit 8711e71f9cbb692d614e6ecf5d51222372f7b77e from qemu
This commit is contained in:
Richard Henderson 2020-05-07 10:05:40 -04:00 committed by Lioncash
parent 07f622e57d
commit b0f6374149
3 changed files with 16 additions and 14 deletions
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10
qemu/target/arm/translate-a64.c
View file

@ -655,7 +655,7 @@ static void clear_vec_high(DisasContext *s, bool is_q, int rd)
tcg_temp_free_i64(tcg_ctx, tcg_zero);
}
if (vsz > 16) {
tcg_gen_gvec_dup8i(tcg_ctx, ofs + 16, vsz - 16, vsz - 16, 0);
tcg_gen_gvec_dup_imm(tcg_ctx, MO_64, ofs + 16, vsz - 16, vsz - 16, 0);
}
}
@ -8053,8 +8053,8 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
/* MOVI or MVNI, with MVNI negation handled above. */
tcg_gen_gvec_dup64i(tcg_ctx, vec_full_reg_offset(s, rd), is_q ? 16 : 8,
vec_full_reg_size(s), imm);
tcg_gen_gvec_dup_imm(tcg_ctx, MO_64, vec_full_reg_offset(s, rd), is_q ? 16 : 8,
vec_full_reg_size(s), imm);
} else {
/* ORR or BIC, with BIC negation to AND handled above. */
if (is_neg) {
@ -10503,8 +10503,8 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
if (is_u) {
if (shift == 8 << size) {
/* Shift count the same size as element size produces zero. */
tcg_gen_gvec_dup8i(tcg_ctx, vec_full_reg_offset(s, rd),
is_q ? 16 : 8, vec_full_reg_size(s), 0);
tcg_gen_gvec_dup_imm(tcg_ctx, size, vec_full_reg_offset(s, rd),
is_q ? 16 : 8, vec_full_reg_size(s), 0);
} else {
gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shri, size);
}

11
qemu/target/arm/translate-sve.c
View file

@ -177,7 +177,7 @@ static void do_dupi_z(DisasContext *s, int rd, uint64_t word)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_dup64i(tcg_ctx, vec_full_reg_offset(s, rd), vsz, vsz, word);
tcg_gen_gvec_dup_imm(tcg_ctx, MO_64, vec_full_reg_offset(s, rd), vsz, vsz, word);
}
/* Invoke a vector expander on two Pregs. */
@ -1550,7 +1550,7 @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
unsigned oprsz = size_for_gvec(setsz / 8);
if (oprsz * 8 == setsz) {
tcg_gen_gvec_dup64i(tcg_ctx, ofs, oprsz, maxsz, word);
tcg_gen_gvec_dup_imm(tcg_ctx, MO_64, ofs, oprsz, maxsz, word);
goto done;
}
}
@ -2159,7 +2159,7 @@ static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a)
unsigned nofs = vec_reg_offset(s, a->rn, index, esz);
tcg_gen_gvec_dup_mem(tcg_ctx, esz, dofs, nofs, vsz, vsz);
} else {
tcg_gen_gvec_dup64i(tcg_ctx, dofs, vsz, vsz, 0);
tcg_gen_gvec_dup_imm(tcg_ctx, esz, dofs, vsz, vsz, 0);
}
}
return true;
@ -3415,9 +3415,8 @@ static bool trans_FDUP(DisasContext *s, arg_FDUP *a)
/* Decode the VFP immediate. */
imm = vfp_expand_imm(a->esz, a->imm);
imm = dup_const(a->esz, imm);
tcg_gen_gvec_dup64i(tcg_ctx, dofs, vsz, vsz, imm);
tcg_gen_gvec_dup_imm(tcg_ctx, a->esz, dofs, vsz, vsz, imm);
}
return true;
}
@ -3432,7 +3431,7 @@ static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a)
unsigned vsz = vec_full_reg_size(s);
int dofs = vec_full_reg_offset(s, a->rd);
tcg_gen_gvec_dup64i(tcg_ctx, dofs, vsz, vsz, dup_const(a->esz, a->imm));
tcg_gen_gvec_dup_imm(tcg_ctx, a->esz, dofs, vsz, vsz, a->imm);
}
return true;
}

9
qemu/target/arm/translate.c
View file

@ -5340,7 +5340,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
MIN(shift, (8 << size) - 1),
vec_size, vec_size);
} else if (shift >= 8 << size) {
tcg_gen_gvec_dup8i(tcg_ctx, rd_ofs, vec_size, vec_size, 0);
tcg_gen_gvec_dup_imm(tcg_ctx, MO_8, rd_ofs, vec_size,
vec_size, 0);
} else {
tcg_gen_gvec_shri(tcg_ctx, size, rd_ofs, rm_ofs, shift,
vec_size, vec_size);
@ -5391,7 +5392,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
* architecturally valid and results in zero.
*/
if (shift >= 8 << size) {
tcg_gen_gvec_dup8i(tcg_ctx, rd_ofs, vec_size, vec_size, 0);
tcg_gen_gvec_dup_imm(tcg_ctx, size, rd_ofs,
vec_size, vec_size, 0);
} else {
tcg_gen_gvec_shli(tcg_ctx, size, rd_ofs, rm_ofs, shift,
vec_size, vec_size);
@ -5737,7 +5739,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
}
tcg_temp_free_i64(tcg_ctx, t64);
} else {
tcg_gen_gvec_dup32i(tcg_ctx, reg_ofs, vec_size, vec_size, imm);
tcg_gen_gvec_dup_imm(tcg_ctx, MO_32, reg_ofs, vec_size,
vec_size, imm);
}
}
}