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arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16

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Backports commit c625ff95070e3ef96bd007de744e1d97c881efeb from qemu
This commit is contained in:
Alex Bennée 2018-03-08 22:45:28 -05:00 committed by Lioncash
parent 068143595e
commit b117df18df
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 7 additions and 0 deletions
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7
qemu/target/arm/translate-a64.c
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@ -11544,6 +11544,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x6f: /* FNEG */ case 0x6f: /* FNEG */
need_fpst = false; need_fpst = false;
break; break;
case 0x7d: /* FRSQRTE */
case 0x7f: /* FSQRT (vector) */ case 0x7f: /* FSQRT (vector) */
break; break;
default: default:
@ -11607,6 +11608,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x6f: /* FNEG */ case 0x6f: /* FNEG */
tcg_gen_xori_i32(tcg_ctx, tcg_res, tcg_op, 0x8000); tcg_gen_xori_i32(tcg_ctx, tcg_res, tcg_op, 0x8000);
break; break;
case 0x7d: /* FRSQRTE */
gen_helper_rsqrte_f16(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus);
break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
} }
@ -11659,6 +11663,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x6f: /* FNEG */ case 0x6f: /* FNEG */
tcg_gen_xori_i32(tcg_ctx, tcg_res, tcg_op, 0x8000); tcg_gen_xori_i32(tcg_ctx, tcg_res, tcg_op, 0x8000);
break; break;
case 0x7d: /* FRSQRTE */
gen_helper_rsqrte_f16(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x7f: /* FSQRT */ case 0x7f: /* FSQRT */
gen_helper_sqrt_f16(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus); gen_helper_sqrt_f16(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus);
break; break;