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https://github.com/yuzu-emu/unicorn.git
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cputlb: Support generating CPU exceptions on memory transaction failures
Call the new cpu_transaction_failed() hook at the places where CPU generated code interacts with the memory system: io_readx() io_writex() get_page_addr_code() Any access from C code (eg via cpu_physical_memory_rw(), address_space_rw(), ld/st_*_phys()) will *not* trigger CPU exceptions via cpu_transaction_failed(). Handling for transactions failures for this kind of call should be done by using a function which returns a MemTxResult and treating the failure case appropriately in the calling code. In an ideal world we would not generate CPU exceptions for instruction fetch failures in get_page_addr_code() but instead wait until the code translation process tried a load and it failed; however that change would require too great a restructuring and redesign to attempt at this point. Backports commit 04e3aabde397e7abc78ba1ce6cbd144d5fbb1722 from qemu
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c44d323359
commit
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@ -298,6 +298,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr)
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ram_addr_t ram_addr;
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ram_addr_t ram_addr;
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CPUState *cpu = ENV_GET_CPU(env);
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CPUState *cpu = ENV_GET_CPU(env);
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CPUIOTLBEntry *iotlbentry;
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CPUIOTLBEntry *iotlbentry;
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hwaddr physaddr;
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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mmu_idx = cpu_mmu_index(env, true);
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mmu_idx = cpu_mmu_index(env, true);
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@ -313,6 +314,19 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr)
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pd = iotlbentry->addr & ~TARGET_PAGE_MASK;
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pd = iotlbentry->addr & ~TARGET_PAGE_MASK;
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mr = iotlb_to_region(cpu, pd, iotlbentry->attrs);
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mr = iotlb_to_region(cpu, pd, iotlbentry->attrs);
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if (memory_region_is_unassigned(cpu->uc, mr)) {
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if (memory_region_is_unassigned(cpu->uc, mr)) {
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/* Give the new-style cpu_transaction_failed() hook first chance
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* to handle this.
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* This is not the ideal place to detect and generate CPU
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* exceptions for instruction fetch failure (for instance
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* we don't know the length of the access that the CPU would
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* use, and it would be better to go ahead and try the access
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* and use the MemTXResult it produced). However it is the
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* simplest place we have currently available for the check.
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*/
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physaddr = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
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cpu_transaction_failed(cpu, physaddr, addr, 0, MMU_INST_FETCH, mmu_idx,
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iotlbentry->attrs, MEMTX_DECODE_ERROR, 0);
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cpu_unassigned_access(cpu, addr, false, true, 0, 4);
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cpu_unassigned_access(cpu, addr, false, true, 0, 4);
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/* The CPU's unassigned access hook might have longjumped out
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/* The CPU's unassigned access hook might have longjumped out
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* with an exception. If it didn't (or there was no hook) then
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* with an exception. If it didn't (or there was no hook) then
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@ -454,12 +468,14 @@ void tlb_unprotect_code(CPUState *cpu, ram_addr_t ram_addr)
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}
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}
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static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
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static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
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int mmu_idx,
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target_ulong addr, uintptr_t retaddr, int size)
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target_ulong addr, uintptr_t retaddr, int size)
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{
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{
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CPUState *cpu = ENV_GET_CPU(env);
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CPUState *cpu = ENV_GET_CPU(env);
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hwaddr physaddr = iotlbentry->addr;
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hwaddr physaddr = iotlbentry->addr;
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MemoryRegion *mr = iotlb_to_region(cpu, physaddr, iotlbentry->attrs);
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MemoryRegion *mr = iotlb_to_region(cpu, physaddr, iotlbentry->attrs);
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uint64_t val;
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uint64_t val;
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MemTxResult r;
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physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
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physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
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cpu->mem_io_pc = retaddr;
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cpu->mem_io_pc = retaddr;
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@ -468,17 +484,24 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
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}
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}
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cpu->mem_io_vaddr = addr;
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cpu->mem_io_vaddr = addr;
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memory_region_dispatch_read(mr, physaddr, &val, size, iotlbentry->attrs);
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r = memory_region_dispatch_read(mr, physaddr,
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&val, size, iotlbentry->attrs);
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if (r != MEMTX_OK) {
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cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_LOAD,
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mmu_idx, iotlbentry->attrs, r, retaddr);
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}
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return val;
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return val;
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}
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}
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static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
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static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
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int mmu_idx,
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uint64_t val, target_ulong addr,
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uint64_t val, target_ulong addr,
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uintptr_t retaddr, int size)
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uintptr_t retaddr, int size)
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{
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{
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CPUState *cpu = ENV_GET_CPU(env);
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CPUState *cpu = ENV_GET_CPU(env);
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hwaddr physaddr = iotlbentry->addr;
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hwaddr physaddr = iotlbentry->addr;
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MemoryRegion *mr = iotlb_to_region(cpu, physaddr, iotlbentry->attrs);
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MemoryRegion *mr = iotlb_to_region(cpu, physaddr, iotlbentry->attrs);
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MemTxResult r;
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physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
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physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
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if (mr != &cpu->uc->io_mem_rom && mr != &cpu->uc->io_mem_notdirty && !cpu->can_do_io) {
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if (mr != &cpu->uc->io_mem_rom && mr != &cpu->uc->io_mem_notdirty && !cpu->can_do_io) {
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@ -487,7 +510,12 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
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cpu->mem_io_vaddr = addr;
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cpu->mem_io_vaddr = addr;
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cpu->mem_io_pc = retaddr;
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cpu->mem_io_pc = retaddr;
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memory_region_dispatch_write(mr, physaddr, val, size, iotlbentry->attrs);
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r = memory_region_dispatch_write(mr, physaddr,
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val, size, iotlbentry->attrs);
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if (r != MEMTX_OK) {
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cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_STORE,
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mmu_idx, iotlbentry->attrs, r, retaddr);
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}
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}
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}
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/* Return true if ADDR is present in the victim tlb, and has been copied
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/* Return true if ADDR is present in the victim tlb, and has been copied
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@ -103,7 +103,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
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uintptr_t retaddr)
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uintptr_t retaddr)
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{
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{
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CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
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CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
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return io_readx(env, iotlbentry, addr, retaddr, DATA_SIZE);
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return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, DATA_SIZE);
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}
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}
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#endif
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#endif
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@ -499,7 +499,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env,
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uintptr_t retaddr)
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uintptr_t retaddr)
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{
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{
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CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
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CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
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return io_writex(env, iotlbentry, val, addr, retaddr, DATA_SIZE);
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return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, DATA_SIZE);
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}
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}
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void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
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void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
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