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target/riscv: fix vill bit index in vtype register

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vill bit is at vtype[XLEN-1].

Backports fbcbafa2c1c33ae6630e7717f7f4141befb5b31a
This commit is contained in:
Frank Chang 2021-03-08 12:13:56 -05:00 committed by Lioncash
parent 61d69c8175
commit b1e52b7958
1 changed files with 1 additions and 1 deletions
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2
qemu/target/riscv/cpu.h
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@ -103,7 +103,7 @@ FIELD(VTYPE, VLMUL, 0, 2)
FIELD(VTYPE, VSEW, 2, 3)
FIELD(VTYPE, VEDIV, 5, 2)
FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 2, 1)
FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
target_ulong gpr[32];