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tcg: Make cpu_gsr a TCGv

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Commit 5d4e1a1081d3f1ec2908ff0eaebe312389971ab4
allows making the type concrete. Also fixes a leak with sparc
This commit is contained in:
Lioncash 2018-02-21 01:17:00 -05:00
parent 4da2fd6407
commit b51f920404
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 9 additions and 10 deletions
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17
qemu/target-sparc/translate.c
View file

@ -1886,7 +1886,7 @@ static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
src2 = gen_load_fpr_D(dc, rs2);
dst = gen_dest_fpr_D(dc, rd);
gen(tcg_ctx, dst, *(TCGv *)tcg_ctx->cpu_gsr, src1, src2);
gen(tcg_ctx, dst, tcg_ctx->cpu_gsr, src1, src2);
gen_store_fpr_D(dc, rd, dst);
}
@ -2572,7 +2572,7 @@ static void gen_alignaddr(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, bool lef
if (left) {
tcg_gen_neg_tl(tcg_ctx, tmp, tmp);
}
tcg_gen_deposit_tl(tcg_ctx, *(TCGv *)tcg_ctx->cpu_gsr, *(TCGv *)tcg_ctx->cpu_gsr, tmp, 0, 3);
tcg_gen_deposit_tl(tcg_ctx, tcg_ctx->cpu_gsr, tcg_ctx->cpu_gsr, tmp, 0, 3);
tcg_temp_free(tcg_ctx, tmp);
}
@ -2886,7 +2886,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
}
gen_store_gpr(dc, rd, *(TCGv *)tcg_ctx->cpu_gsr);
gen_store_gpr(dc, rd, tcg_ctx->cpu_gsr);
break;
case 0x16: /* Softint */
tcg_gen_ext_i32_tl(tcg_ctx, cpu_dst, tcg_ctx->cpu_softint);
@ -3783,7 +3783,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
}
tcg_gen_xor_tl(tcg_ctx, *(TCGv *)tcg_ctx->cpu_gsr, cpu_src1, cpu_src2);
tcg_gen_xor_tl(tcg_ctx, tcg_ctx->cpu_gsr, cpu_src1, cpu_src2);
break;
case 0x14: /* Softint set */
if (!supervisor(dc))
@ -4294,7 +4294,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
tcg_gen_add_tl(tcg_ctx, cpu_dst, cpu_src1, cpu_src2);
tcg_gen_deposit_tl(tcg_ctx, *(TCGv *)tcg_ctx->cpu_gsr, *(TCGv *)tcg_ctx->cpu_gsr, cpu_dst, 32, 32);
tcg_gen_deposit_tl(tcg_ctx, tcg_ctx->cpu_gsr, tcg_ctx->cpu_gsr, cpu_dst, 32, 32);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x020: /* VIS I fcmple16 */
@ -4389,14 +4389,14 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs2);
cpu_dst_32 = gen_dest_fpr_F(dc);
gen_helper_fpack16(tcg_ctx, cpu_dst_32, *(TCGv *)tcg_ctx->cpu_gsr, cpu_src1_64);
gen_helper_fpack16(tcg_ctx, cpu_dst_32, tcg_ctx->cpu_gsr, cpu_src1_64);
gen_store_fpr_F(dc, rd, cpu_dst_32);
break;
case 0x03d: /* VIS I fpackfix */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs2);
cpu_dst_32 = gen_dest_fpr_F(dc);
gen_helper_fpackfix(tcg_ctx, cpu_dst_32, *(TCGv *)tcg_ctx->cpu_gsr, cpu_src1_64);
gen_helper_fpackfix(tcg_ctx, cpu_dst_32, tcg_ctx->cpu_gsr, cpu_src1_64);
gen_store_fpr_F(dc, rd, cpu_dst_32);
break;
case 0x03e: /* VIS I pdist */
@ -5533,8 +5533,7 @@ void gen_intermediate_code_init(CPUSPARCState *env)
tcg_ctx->cpu_fprs = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, fprs),
"fprs");
tcg_ctx->cpu_gsr = g_malloc0(sizeof(TCGv));
*(TCGv *)tcg_ctx->cpu_gsr = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, gsr),
tcg_ctx->cpu_gsr = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, gsr),
"gsr");
tcg_ctx->cpu_tick_cmpr = g_malloc0(sizeof(TCGv));

2
qemu/tcg/tcg.h
View file

@ -838,7 +838,7 @@ struct TCGContext {
TCGv cpu_y;
TCGv cpu_tbr;
TCGv cpu_cond;
void *cpu_gsr;
TCGv cpu_gsr;
void *cpu_tick_cmpr, *cpu_stick_cmpr, *cpu_hstick_cmpr;
void *cpu_hintp, *cpu_htba, *cpu_hver, *cpu_ssr, *cpu_ver;
void *cpu_wim;