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target/arm: Implement FDUP/DUP

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Backports commit ed49196125360c037d7f23c1c315a85cc234e72d from qemu
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Richard Henderson 2018-06-15 13:56:01 -04:00 committed by Lioncash
parent 496bb35c97
commit b5352c6ba1
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 47 additions and 0 deletions
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8
qemu/target/arm/sve.decode
View file

@ -614,6 +614,14 @@ CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000
# SVE integer compare scalar count and limit
WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4
### SVE Integer Wide Immediate - Unpredicated Group
# SVE broadcast floating-point immediate (unpredicated)
FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5
# SVE broadcast integer immediate (unpredicated)
DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
### SVE Memory - 32-bit Gather and Unsized Contiguous Group
# SVE load predicate register

39
qemu/target/arm/translate-sve.c
View file

@ -3306,6 +3306,45 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a, uint32_t insn)
return true;
}
/*
*** SVE Integer Wide Immediate - Unpredicated Group
*/
static bool trans_FDUP(DisasContext *s, arg_FDUP *a, uint32_t insn)
{
if (a->esz == 0) {
return false;
}
if (sve_access_check(s)) {
TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned vsz = vec_full_reg_size(s);
int dofs = vec_full_reg_offset(s, a->rd);
uint64_t imm;
/* Decode the VFP immediate. */
imm = vfp_expand_imm(a->esz, a->imm);
imm = dup_const(a->esz, imm);
tcg_gen_gvec_dup64i(tcg_ctx, dofs, vsz, vsz, imm);
}
return true;
}
static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a, uint32_t insn)
{
if (a->esz == 0 && extract32(insn, 13, 1)) {
return false;
}
if (sve_access_check(s)) {
TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned vsz = vec_full_reg_size(s);
int dofs = vec_full_reg_offset(s, a->rd);
tcg_gen_gvec_dup64i(tcg_ctx, dofs, vsz, vsz, dup_const(a->esz, a->imm));
}
return true;
}
/*
*** SVE Memory - 32-bit Gather and Unsized Contiguous Group
*/