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target/arm: Split out vfp_expand_imm
Backports commit e90a99fe6bde9b85bff8c052ade51520f20d9bce from qemu.
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@ -4712,6 +4712,33 @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
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}
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}
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/* The imm8 encodes the sign bit, enough bits to represent an exponent in
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* the range 01....1xx to 10....0xx, and the most significant 4 bits of
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* the mantissa; see VFPExpandImm() in the v8 ARM ARM.
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*/
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static uint64_t vfp_expand_imm(int size, uint8_t imm8)
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{
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uint64_t imm;
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switch (size) {
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case MO_64:
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imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
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(extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |
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extract32(imm8, 0, 6);
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imm <<= 48;
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break;
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case MO_32:
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imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
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(extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |
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(extract32(imm8, 0, 6) << 3);
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imm <<= 16;
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break;
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default:
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g_assert_not_reached();
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}
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return imm;
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}
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/* C3.6.28 Floating point immediate
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* 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
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* +---+---+---+-----------+------+---+------------+-------+------+------+
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@ -4736,22 +4763,7 @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
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return;
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}
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/* The imm8 encodes the sign bit, enough bits to represent
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* an exponent in the range 01....1xx to 10....0xx,
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* and the most significant 4 bits of the mantissa; see
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* VFPExpandImm() in the v8 ARM ARM.
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*/
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if (is_double) {
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imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
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(extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |
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extract32(imm8, 0, 6);
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imm <<= 48;
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} else {
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imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
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(extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |
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(extract32(imm8, 0, 6) << 3);
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imm <<= 16;
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}
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imm = vfp_expand_imm(MO_32 + is_double, imm8);
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tcg_res = tcg_const_i64(tcg_ctx, imm);
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write_fp_dreg(s, rd, tcg_res);
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