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target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6

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Implement the relationship between CP0.Status.KX, SX and UX. It should not
be possible to set UX bit if SX is 0, the same applies for setting SX if
KX is 0.

Backports commit 2dcf7908d9e0274c08911400beb7ed14276bb170 from qemu
This commit is contained in:
Leon Alrae 2018-02-17 14:30:18 -05:00 committed by Lioncash
parent cab0efb406
commit b59c9c0e2c
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 6 additions and 1 deletions
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7
qemu/target-mips/cpu.h
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@ -1007,7 +1007,12 @@ static inline void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
if (env->insn_flags & ISA_MIPS32R6) { if (env->insn_flags & ISA_MIPS32R6) {
bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3; bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
#if defined(TARGET_MIPS64)
uint32_t ksux = (1 << CP0St_KX) & val;
ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
val = (val & ~(7 << CP0St_UX)) | ksux;
#endif
if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) { if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
mask &= ~(3 << CP0St_KSU); mask &= ~(3 << CP0St_KSU);
} }