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target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2

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The EL1&0 regime is the only one that uses 2-stage translation.

Backports commit 97fa9350017e647151dd1dc212f1bbca0294dba7 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 14:15:33 -04:00 committed by Lioncash
parent ec05f22e82
commit b62b4c4f35
5 changed files with 35 additions and 32 deletions
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4
qemu/target/arm/cpu.h
View file

@ -2806,7 +2806,7 @@ typedef enum ARMMMUIdx {
ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A,
ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A,
ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A,
ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_A,
ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M,
ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M,
ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M,
@ -2832,7 +2832,7 @@ typedef enum ARMMMUIdxBit {
ARMMMUIdxBit_S1E3 = 1 << 3, ARMMMUIdxBit_S1E3 = 1 << 3,
ARMMMUIdxBit_S1SE0 = 1 << 4, ARMMMUIdxBit_S1SE0 = 1 << 4,
ARMMMUIdxBit_S1SE1 = 1 << 5, ARMMMUIdxBit_S1SE1 = 1 << 5,
ARMMMUIdxBit_S2NS = 1 << 6, ARMMMUIdxBit_Stage2 = 1 << 6,
ARMMMUIdxBit_MUser = 1 << 0, ARMMMUIdxBit_MUser = 1 << 0,
ARMMMUIdxBit_MPriv = 1 << 1, ARMMMUIdxBit_MPriv = 1 << 1,
ARMMMUIdxBit_MUserNegPri = 1 << 2, ARMMMUIdxBit_MUserNegPri = 1 << 2,

57
qemu/target/arm/helper.c
View file

@ -515,7 +515,7 @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
tlb_flush_by_mmuidx(cs, tlb_flush_by_mmuidx(cs,
ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_1 |
ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_E10_0 |
ARMMMUIdxBit_S2NS); ARMMMUIdxBit_Stage2);
} }
static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -528,7 +528,7 @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
tlb_flush_by_mmuidx_all_cpus_synced(cs, tlb_flush_by_mmuidx_all_cpus_synced(cs,
ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_1 |
ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_E10_0 |
ARMMMUIdxBit_S2NS); ARMMMUIdxBit_Stage2);
#endif #endif
} }
@ -550,7 +550,7 @@ static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,
pageaddr = sextract64(value << 12, 0, 40); pageaddr = sextract64(value << 12, 0, 40);
tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
} }
static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -568,7 +568,7 @@ static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
pageaddr = sextract64(value << 12, 0, 40); pageaddr = sextract64(value << 12, 0, 40);
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
ARMMMUIdxBit_S2NS); ARMMMUIdxBit_Stage2);
#endif #endif
} }
@ -3354,12 +3354,15 @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
ARMCPU *cpu = env_archcpu(env); ARMCPU *cpu = env_archcpu(env);
CPUState *cs = CPU(cpu); CPUState *cs = CPU(cpu);
/* Accesses to VTTBR may change the VMID so we must flush the TLB. */ /*
* A change in VMID to the stage2 page table (Stage2) invalidates
* the combined stage 1&2 tlbs (EL10_1 and EL10_0).
*/
if (raw_read(env, ri) != value) { if (raw_read(env, ri) != value) {
tlb_flush_by_mmuidx(cs, tlb_flush_by_mmuidx(cs,
ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_1 |
ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_E10_0 |
ARMMMUIdxBit_S2NS); ARMMMUIdxBit_Stage2);
raw_write(env, ri, value); raw_write(env, ri, value);
} }
} }
@ -3760,7 +3763,7 @@ static int alle1_tlbmask(CPUARMState *env)
if (arm_is_secure_below_el3(env)) { if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
} else if (arm_feature(env, ARM_FEATURE_EL2)) { } else if (arm_feature(env, ARM_FEATURE_EL2)) {
return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_S2NS; return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stage2;
} else { } else {
return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0; return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0;
} }
@ -3933,7 +3936,7 @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
pageaddr = sextract64(value << 12, 0, 48); pageaddr = sextract64(value << 12, 0, 48);
tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
} }
static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -3951,7 +3954,7 @@ static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
pageaddr = sextract64(value << 12, 0, 48); pageaddr = sextract64(value << 12, 0, 48);
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
ARMMMUIdxBit_S2NS); ARMMMUIdxBit_Stage2);
#endif #endif
} }
@ -8547,7 +8550,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
{ {
switch (mmu_idx) { switch (mmu_idx) {
case ARMMMUIdx_S2NS: case ARMMMUIdx_Stage2:
case ARMMMUIdx_S1E2: case ARMMMUIdx_S1E2:
return 2; return 2;
case ARMMMUIdx_S1E3: case ARMMMUIdx_S1E3:
@ -8602,7 +8605,7 @@ static inline bool regime_translation_disabled(CPUARMState *env,
} }
} }
if (mmu_idx == ARMMMUIdx_S2NS) { if (mmu_idx == ARMMMUIdx_Stage2) {
/* HCR.DC means HCR.VM behaves as 1 */ /* HCR.DC means HCR.VM behaves as 1 */
return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) == 0; return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) == 0;
} }
@ -8633,7 +8636,7 @@ static inline bool regime_translation_big_endian(CPUARMState *env,
static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
int ttbrn) int ttbrn)
{ {
if (mmu_idx == ARMMMUIdx_S2NS) { if (mmu_idx == ARMMMUIdx_Stage2) {
return env->cp15.vttbr_el2; return env->cp15.vttbr_el2;
} }
if (ttbrn == 0) { if (ttbrn == 0) {
@ -8648,7 +8651,7 @@ static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
/* Return the TCR controlling this translation regime */ /* Return the TCR controlling this translation regime */
static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
{ {
if (mmu_idx == ARMMMUIdx_S2NS) { if (mmu_idx == ARMMMUIdx_Stage2) {
return &env->cp15.vtcr_el2; return &env->cp15.vtcr_el2;
} }
return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
@ -8843,7 +8846,7 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
bool have_wxn; bool have_wxn;
int wxn = 0; int wxn = 0;
assert(mmu_idx != ARMMMUIdx_S2NS); assert(mmu_idx != ARMMMUIdx_Stage2);
user_rw = simple_ap_to_rw_prot_is_user(ap, true); user_rw = simple_ap_to_rw_prot_is_user(ap, true);
if (is_user) { if (is_user) {
@ -8936,7 +8939,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
ARMMMUFaultInfo *fi) ARMMMUFaultInfo *fi)
{ {
if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) && if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) &&
!regime_translation_disabled(env, ARMMMUIdx_S2NS)) { !regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
target_ulong s2size; target_ulong s2size;
hwaddr s2pa; hwaddr s2pa;
int s2prot; int s2prot;
@ -8953,7 +8956,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
pcacheattrs = &cacheattrs; pcacheattrs = &cacheattrs;
} }
ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_Stage2, &s2pa,
&txattrs, &s2prot, &s2size, fi, pcacheattrs); &txattrs, &s2prot, &s2size, fi, pcacheattrs);
if (ret) { if (ret) {
assert(fi->type != ARMFault_None); assert(fi->type != ARMFault_None);
@ -9429,7 +9432,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
tsz = extract32(tcr, 0, 6); tsz = extract32(tcr, 0, 6);
using64k = extract32(tcr, 14, 1); using64k = extract32(tcr, 14, 1);
using16k = extract32(tcr, 15, 1); using16k = extract32(tcr, 15, 1);
if (mmu_idx == ARMMMUIdx_S2NS) { if (mmu_idx == ARMMMUIdx_Stage2) {
/* VTCR_EL2 */ /* VTCR_EL2 */
tbi = tbid = hpd = false; tbi = tbid = hpd = false;
} else { } else {
@ -9490,7 +9493,7 @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
int select, tsz; int select, tsz;
bool epd, hpd; bool epd, hpd;
if (mmu_idx == ARMMMUIdx_S2NS) { if (mmu_idx == ARMMMUIdx_Stage2) {
/* VTCR */ /* VTCR */
bool sext = extract32(tcr, 4, 1); bool sext = extract32(tcr, 4, 1);
bool sign = extract32(tcr, 3, 1); bool sign = extract32(tcr, 3, 1);
@ -9594,7 +9597,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
level = 1; level = 1;
/* There is no TTBR1 for EL2 */ /* There is no TTBR1 for EL2 */
ttbr1_valid = (el != 2); ttbr1_valid = (el != 2);
addrsize = (mmu_idx == ARMMMUIdx_S2NS ? 40 : 32); addrsize = (mmu_idx == ARMMMUIdx_Stage2 ? 40 : 32);
inputsize = addrsize - param.tsz; inputsize = addrsize - param.tsz;
} }
@ -9648,7 +9651,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
goto do_fault; goto do_fault;
} }
if (mmu_idx != ARMMMUIdx_S2NS) { if (mmu_idx != ARMMMUIdx_Stage2) {
/* /*
* The starting level depends on the virtual address size (which can * The starting level depends on the virtual address size (which can
* be up to 48 bits) and the translation granule size. It indicates * be up to 48 bits) and the translation granule size. It indicates
@ -9754,7 +9757,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
attrs = extract64(descriptor, 2, 10) attrs = extract64(descriptor, 2, 10)
| (extract64(descriptor, 52, 12) << 10); | (extract64(descriptor, 52, 12) << 10);
if (mmu_idx == ARMMMUIdx_S2NS) { if (mmu_idx == ARMMMUIdx_Stage2) {
/* Stage 2 table descriptors do not include any attribute fields */ /* Stage 2 table descriptors do not include any attribute fields */
break; break;
} }
@ -9787,7 +9790,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
ap = extract32(attrs, 4, 2); ap = extract32(attrs, 4, 2);
xn = extract32(attrs, 12, 1); xn = extract32(attrs, 12, 1);
if (mmu_idx == ARMMMUIdx_S2NS) { if (mmu_idx == ARMMMUIdx_Stage2) {
ns = true; ns = true;
*prot = get_S2prot(env, ap, xn); *prot = get_S2prot(env, ap, xn);
} else { } else {
@ -9815,7 +9818,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
} }
if (cacheattrs != NULL) { if (cacheattrs != NULL) {
if (mmu_idx == ARMMMUIdx_S2NS) { if (mmu_idx == ARMMMUIdx_Stage2) {
cacheattrs->attrs = convert_stage2_attrs(env, cacheattrs->attrs = convert_stage2_attrs(env,
extract32(attrs, 0, 4)); extract32(attrs, 0, 4));
} else { } else {
@ -9836,7 +9839,7 @@ do_fault:
fi->type = fault_type; fi->type = fault_type;
fi->level = level; fi->level = level;
/* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS); fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_Stage2);
return true; return true;
} }
@ -10646,13 +10649,13 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
prot, page_size, fi, cacheattrs); prot, page_size, fi, cacheattrs);
/* If S1 fails or S2 is disabled, return early. */ /* If S1 fails or S2 is disabled, return early. */
if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
*phys_ptr = ipa; *phys_ptr = ipa;
return ret; return ret;
} }
/* S1 is done. Now do S2 translation. */ /* S1 is done. Now do S2 translation. */
ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS, ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_Stage2,
phys_ptr, attrs, &s2_prot, phys_ptr, attrs, &s2_prot,
page_size, fi, page_size, fi,
cacheattrs != NULL ? &cacheattrs2 : NULL); cacheattrs != NULL ? &cacheattrs2 : NULL);
@ -10696,7 +10699,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
* Fast Context Switch Extension. This doesn't exist at all in v8. * Fast Context Switch Extension. This doesn't exist at all in v8.
* In v7 and earlier it affects all stage 1 translations. * In v7 and earlier it affects all stage 1 translations.
*/ */
if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS if (address < 0x02000000 && mmu_idx != ARMMMUIdx_Stage2
&& !arm_feature(env, ARM_FEATURE_V8)) { && !arm_feature(env, ARM_FEATURE_V8)) {
if (regime_el(env, mmu_idx) == 3) { if (regime_el(env, mmu_idx) == 3) {
address += env->cp15.fcseidr_s; address += env->cp15.fcseidr_s;

2
qemu/target/arm/internals.h
View file

@ -815,7 +815,7 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
case ARMMMUIdx_S1NSE0: case ARMMMUIdx_S1NSE0:
case ARMMMUIdx_S1NSE1: case ARMMMUIdx_S1NSE1:
case ARMMMUIdx_S1E2: case ARMMMUIdx_S1E2:
case ARMMMUIdx_S2NS: case ARMMMUIdx_Stage2:
case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MPrivNegPri:
case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MUserNegPri:
case ARMMMUIdx_MPriv: case ARMMMUIdx_MPriv:

2
qemu/target/arm/translate-a64.c
View file

@ -120,7 +120,7 @@ static inline int get_a64_user_mem_index(DisasContext *s)
case ARMMMUIdx_S1SE1: case ARMMMUIdx_S1SE1:
useridx = ARMMMUIdx_S1SE0; useridx = ARMMMUIdx_S1SE0;
break; break;
case ARMMMUIdx_S2NS: case ARMMMUIdx_Stage2:
g_assert_not_reached(); g_assert_not_reached();
default: default:
useridx = s->mmu_idx; useridx = s->mmu_idx;

2
qemu/target/arm/translate.c
View file

@ -166,7 +166,7 @@ static inline int get_a32_user_mem_index(DisasContext *s)
case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSUserNegPri:
case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSPrivNegPri:
return arm_to_core_mmu_idx(ARMMMUIdx_MSUserNegPri); return arm_to_core_mmu_idx(ARMMMUIdx_MSUserNegPri);
case ARMMMUIdx_S2NS: case ARMMMUIdx_Stage2:
default: default:
g_assert_not_reached(); g_assert_not_reached();
} }