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target/arm: use arm_hcr_el2_eff() where applicable
This will simplify accessing HCR conditionally in secure state. Backports e04a5752cb03e066d7b1e583e340c7982fcd5e4e
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@ -4125,16 +4125,16 @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
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static int vae1_tlbmask(CPUARMState *env)
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{
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/* Since we exclude secure first, we may read HCR_EL2 directly. */
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if (arm_is_secure_below_el3(env)) {
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return ARMMMUIdxBit_SE10_1 |
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ARMMMUIdxBit_SE10_1_PAN |
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ARMMMUIdxBit_SE10_0;
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} else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE))
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== (HCR_E2H | HCR_TGE)) {
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uint64_t hcr = arm_hcr_el2_eff(env);
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if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
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return ARMMMUIdxBit_E20_2 |
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ARMMMUIdxBit_E20_2_PAN |
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ARMMMUIdxBit_E20_0;
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} else if (arm_is_secure_below_el3(env)) {
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return ARMMMUIdxBit_SE10_1 |
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ARMMMUIdxBit_SE10_1_PAN |
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ARMMMUIdxBit_SE10_0;
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} else {
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return ARMMMUIdxBit_E10_1 |
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ARMMMUIdxBit_E10_1_PAN |
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@ -9680,6 +9680,8 @@ static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
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static inline bool regime_translation_disabled(CPUARMState *env,
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ARMMMUIdx mmu_idx)
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{
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uint64_t hcr_el2;
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if (arm_feature(env, ARM_FEATURE_M)) {
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switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] &
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(R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) {
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@ -9699,19 +9701,21 @@ static inline bool regime_translation_disabled(CPUARMState *env,
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}
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}
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hcr_el2 = arm_hcr_el2_eff(env);
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if (mmu_idx == ARMMMUIdx_Stage2) {
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/* HCR.DC means HCR.VM behaves as 1 */
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return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) == 0;
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return (hcr_el2 & (HCR_DC | HCR_VM)) == 0;
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}
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if (env->cp15.hcr_el2 & HCR_TGE) {
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if (hcr_el2 & HCR_TGE) {
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/* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
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if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) {
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return true;
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}
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}
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if ((env->cp15.hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) {
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if ((hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) {
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/* HCR.DC means SCTLR_EL1.M behaves as 0 */
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return true;
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}
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@ -10072,7 +10076,8 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
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fi->s1ptw = true;
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return ~0;
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}
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if ((env->cp15.hcr_el2 & HCR_PTW) && (cacheattrs.attrs & 0xf0) == 0) {
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if ((arm_hcr_el2_eff(env) & HCR_PTW) &&
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(cacheattrs.attrs & 0xf0) == 0) {
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/*
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* PTW set and S1 walk touched S2 Device memory:
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* generate Permission fault.
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@ -10509,7 +10514,7 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
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uint8_t hihint = 0, lohint = 0;
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if (hiattr != 0) { /* normal memory */
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if ((env->cp15.hcr_el2 & HCR_CD) != 0) { /* cache disabled */
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if (arm_hcr_el2_eff(env) & HCR_CD) { /* cache disabled */
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hiattr = loattr = 1; /* non-cacheable */
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} else {
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if (hiattr != 1) { /* Write-through or write-back */
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@ -11835,7 +11840,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
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}
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/* Combine the S1 and S2 cache attributes. */
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if (env->cp15.hcr_el2 & HCR_DC) {
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if (arm_hcr_el2_eff(env) & HCR_DC) {
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/*
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* HCR.DC forces the first stage attributes to
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* Normal Non-Shareable,
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