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target/arm: Forbid unprivileged mode for M Baseline
MSR handling is the only place where CONTROL.nPRIV is modified. Backports commit def183446cebc0090f6d885383a6502302249f33 from qemu
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@ -9933,8 +9933,10 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
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write_v7m_control_spsel_for_secstate(env,
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val & R_V7M_CONTROL_SPSEL_MASK,
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M_REG_NS);
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env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK;
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env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK;
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if (arm_feature(env, ARM_FEATURE_M_MAIN)) {
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env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK;
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env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK;
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}
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return;
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case 0x98: /* SP_NS */
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{
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@ -10034,8 +10036,10 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
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!arm_v7m_is_handler_mode(env)) {
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write_v7m_control_spsel(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);
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}
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env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK;
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env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;
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if (arm_feature(env, ARM_FEATURE_M_MAIN)) {
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env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK;
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env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;
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}
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break;
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default:
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bad_reg:
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