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tcg: Check for watchpoints in probe_write()

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Let size > 0 indicate a promise to write to those bytes.
Check for write watchpoints in the probed range.

Backports commit 03a981893c99faba84bb373976796ad7dce0aecc from qemu
This commit is contained in:
David Hildenbrand 2020-01-14 07:00:55 -05:00 committed by Lioncash
parent 07f30382c0
commit b732ad9eba
1 changed files with 13 additions and 2 deletions
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15
qemu/accel/tcg/cputlb.c
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@ -714,13 +714,24 @@ void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
{ {
uintptr_t index = tlb_index(env, mmu_idx, addr); uintptr_t index = tlb_index(env, mmu_idx, addr);
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
target_ulong tlb_addr = tlb_addr_write(entry);
if (!tlb_hit(tlb_addr_write(entry), addr)) { if (unlikely(!tlb_hit(tlb_addr, addr))) {
/* TLB entry is for a different page */
if (!VICTIM_TLB_HIT(addr_write, addr)) { if (!VICTIM_TLB_HIT(addr_write, addr)) {
tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE, tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE,
mmu_idx, retaddr); mmu_idx, retaddr);
/* TLB resize via tlb_fill may have moved the entry. */
index = tlb_index(env, mmu_idx, addr);
entry = tlb_entry(env, mmu_idx, addr);
} }
tlb_addr = tlb_addr_write(entry);
}
/* Handle watchpoints. */
if ((tlb_addr & TLB_WATCHPOINT) && size > 0) {
cpu_check_watchpoint(env_cpu(env), addr, size,
env->iotlb[mmu_idx][index].attrs,
BP_MEM_WRITE, retaddr);
} }
} }